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參數(shù)資料
| 型號： | MSM548332 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 278,400-Word×12-Bit Field Memory(278,400字×12位場存儲器) |
| 中文描述： | 27.84萬詞× 12位場存儲器（278400字× 12位場存儲器） |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 245K |
| 代理商： | MSM548332 |
Semiconductor
MSM548332
7/23
OPERATION MODE
Write
1. Write operation
Before the write operation begins, X address (or line address) must be input to set the initial
bit address for the following serial write access. When WE and IE are high, a set of serial 12-
bit -width write data on DIN0-11 is written into write registers attached to the DRAM memory
arrays temporarily on the rising edge of WCLK.
Following 12-bit-width serial input data is written into the memory locations in the write
register designated by an internal write address pointer which is advanced by WCLK. This
enables continuous serial write on a line. When write clock WCLK and read clock RCLK are
tied together and are controlled by a common clock or CLK, more than two MSM548332s can
be cascaded directly without any delay devices between the MSM548332s because the read
timing is delayed by one CLK cycle to the write timing. When the write operation on a line is
terminated, be sure to perform a write transfer operation by WR/TR in order to store the
written data in the write registers to the corresponding memory cells in the DRAM memory
arrays.
2. Write address pointer increment operation
The write address pointer is incremented synchronously with WCLK when WE is high.
WE
H
H
L
IE
H
L
—
WCLK Rise
Internal Write
Address Pointer
Data Input
Incremented
Inputted
Not Inputted
Stopped
Relationship between the WE and IE input levels,
Write Address pointer, and data input status
When WE and IE are high, the write operation is enabled.
If IE level goes low while WCLK is active, the write operation is halted but the write address
pointer will continue to advance. That is, IE enables a write mask function. When WE goes
low, the write address pointer stops without WCLK.
Read
1. Read operation
Before the read operation begins, the X address (or line address) must be input for setting
initial bit address for the following serial read access.
When both RE and OE are high, a set of serial 12-bit-width read data on DO0-11 pins is read
from read registers attached to DRAM memory arrays on the rising edge of RCLK.
Each access time is specified by the rising edges of RCLK.
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