參數(shù)資料
型號: MSC8144EVT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 63/80頁
文件大?。?/td> 1251K
代理商: MSC8144EVT800B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Hardware Design Considerations
Freescale Semiconductor
66
Figure 43. PLL Supplies
3.3
Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
Keep clock and timing signal paths as short as possible and route with 50
Ω impedance.
Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resistor value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
Note:
See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.
3.4
Connectivity Guidelines
Note:
Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal
connections in this discussion.
First, select the pin multiplexing mode to allocate the required I/O signals. Then use the guidelines presented in the following
subsections for board design and connections. The following conventions are used in describing the connectivity requirements:
1.
GND indicates using a 10 k
Ω pull-down resistor (recommended) or a direct connection to the ground plane. Direct
connections to the ground plane may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
2.
VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.
Direct connections to the supply may yield DC current up to 50mA through the I/O supply that adds to overall power
consumption.
3.
Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.
MSC8144E
VDDPLL0
10
Ω
2.2
μF
2.2
μF
VDDPLL0
10
Ω
2.2
μF
2.2
μF
VDDPLL0
10
Ω
2.2
μF
2.2
μF
Voltage Regulator
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