參數(shù)資料
型號： MSC8144EVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù)： 62/80頁
文件大?。?/td> 1251K
代理商： MSC8144EVT800B
Hardware Design Considerations
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
65
The following supplies should rise before any other supplies in any sequence
VDD and VDDPLL coupled together
VDDM3
After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 42):
VDDGE1
VDDGE2
VDDIO
VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR.
VDDM3IO
V25M3
Note:
1.
This recommended power sequencing is different from the MSC8122/MSC8126.
2.
If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.
3.
If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.
4.
If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.
5.
If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.
6.
If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.
3.1.2
Start-Up Timing
Section 2.6.1 describes the start-up timing.
3.2
Each PLL supply must have an external RC filter for the VDDPLL input. The filter is a 10 Ω resistor in series with two 2.2 μF,
low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage
regulator) as long as the external RC filter is applied to each PLL separately (see Figure 43). For optimal noise filtering, place
the circuit as close as possible to its VDDPLL inputs. These traces should be short and direct.
Figure 42. VDDM3, VDDM3IO and V25M3 Power-on Sequence
VDDM3, VDD, and VDDPLL
90%
I/O supplies
相關(guān)PDF資料
PDF描述
MSC8144ETVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144VT800B 133 MHz, OTHER DSP, PBGA783
MSC8144SVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144TVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144SVT1000B 133 MHz, OTHER DSP, PBGA783
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8144SVT1000A 功能描述:IC DSP QUAD 1GHZ 783FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8144SVT1000B 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E
MSC8144SVT800A 功能描述:IC DSP QUAD 800MHZ 783FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8144SVT800B 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144TVT1000A 功能描述:IC DSP QUAD 1GHZ 783FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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