參數(shù)資料
型號(hào)： MSC8144EVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù)： 54/80頁
文件大?。?/td> 1251K
代理商： MSC8144EVT800B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
58
Figure 30. SMII Mode Signal Timing
2.6.10.6
RGMII AC Timing Specifications
Table 45 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 46 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Table 45. RGMII with On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKEWT
-0.5
—
0.5
ns
Data to clock input skew (at receiver) 2
tSKEWR
0.9
—
2.6
ns
Clock cycle duration 3
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T 4, 5
tRGTH/tRGT
45
50
55
%
Duty cycle for 10BASE-T and 100BASE-TX 3, 5
tRGTH/tRGT
40
50
60
%
Rise time (20%–80%)
tRGTR
—
0.75
ns
Fall time (20%–80%)
tRGTF
—
0.75
ns
GTX_CLK125 reference clock period
tG12
6
—8.0
—
ns
GTX_CLK125 reference clock duty cycle
tG125H/tG125
45
—
55
%
Notes:
1.
At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2.
This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will
be added to the associated clock signal.
3.
For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.
4.
Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5.
Duty cycle reference is LVdd/2.
6.
This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7.
GCR4 should be programmed as 0x00001004.
Table 46. RGMII with No On-Board Delay AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKEWT
–2.6
—
–0.9
ns
Data to clock input skew (at receiver) 2
tSKEWR
–0.5
—
0.5
ns
Notes:
1.
At recommended operating conditions with LVDD of 2.5 V +/- 5%.
2.
This implies that PC board design will require clocks to be routed with no additional trace delay
3.
GCR4 should be programmed as 0x0004C130.
Valid
ETHCLOCK
ETHSYNC_IN
ETHRXD
ETHSYNC
ETHTXD
Valid
tSMXR
tSMDXKH
tSMDVKH
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