參數(shù)資料
型號(hào): MSC8144EVT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁(yè)數(shù): 37/80頁(yè)
文件大小: 1251K
代理商: MSC8144EVT800B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freescale Semiconductor
42
Figure 10 provides the AC test load for the DDR bus.
2.6.5
Serial RapidIO Timing and SGMII Timing
2.6.5.1
AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK
Table 24 lists AC signal specifications.
2.6.5.2
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description and specification of differential
signals. Figure 11 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)
or a receiver input (RD and RD). Each signal swings between voltage levels A and B, where A > B.
Note:
This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/
SRIO_RXD/SRIO_RXD respectively.
Figure 10. DDR AC Test Load
Table 24. SDn_REF_CLK and SDn_REF_CLK AC Signal Specifications
Parameter Description
Symbol
Min
Typical
Max
Units
Comments
REFCLK cycle time
tREF
10 (8, 6.4)
ns
8 ns applies only to serial RapidIO system
with 125-MHz reference clock. 6.4 ns
applies only to serial RapidIO systems with
a 156.25 MHz reference clock.
Note:
SGMII uses the 8 ns (125 MHz)
value only.
Figure 11. Differential VPP of Transmitter or Receiver
Output
Z0 = 50 Ω
RL = 50 Ω
VDDDDR/2
Differential Peak-Peak = 2
× (A – B)
A
TD or RD
B
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