參數(shù)資料
型號: MSC1211Y3PAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 4/111頁
文件大小: 1113K
代理商: MSC1211Y3PAGRG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
101
One Millisecond Timer High Byte (MSECH)
7
6
5
4
3
2
1
0
Reset Value
SFR FDh
MSECH7
MSECH6
MSECH5
MSECH4
MSECH3
MSECH2
MSECH1
MSECH0
0Fh
MSECH70 One Millisecond Timer High Byte. This value in combination with the previous register is used to create a 1ms clock.
bits 70
1ms = (MSECH
256 + MSECL + 1) tCLK.
One Hundred Millisecond Timer (HMSEC)
7
6
5
4
3
2
1
0
Reset Value
SFR FEh
WRT
HMSEC6
HMSEC5
HMSEC4
HMSEC3
HMSEC2
HMSEC1
HMSEC0
63h
WRT
Write Control. Determines whether to write the value immediately or wait until the current count is finished. Read = 0.
bit 7
0 = Delay Write Operation. The MSINT value is loaded when the current count expires.
1 = Write Immediately. The MSINT counter is loaded once the CPU completes the write operation.
HMSEC60 One Hundred Millisecond. This clock divides the 1ms clock to create a 100ms clock.
bits 60
100ms = (MSECH
256 + MSECL + 1) (HMSEC + 1) tCLK.
Watchdog Timer (WDTCON)
7
6
5
4
3
2
1
0
Reset Value
SFR FFh
EWDT
DWDT
RWDT
WDCNT4
WDCNT3
WDCNT2
WDCNT1
WDCNT0
00h
EWDT
Enable Watchdog (R/W).
bit 7
Write 1/Write 0 sequence sets the Watchdog Enable Counting bit.
DWDT
Disable Watchdog (R/W).
bit 6
Write 1/Write 0 sequence clears the Watchdog Enable Counting bit.
RWDT
Reset Watchdog (R/W).
bit 5
Write 1/Write 0 sequence restarts the Watchdog Counter.
WDCNT40 Watchdog Count (R/W).
bits 40
Watchdog expires in (WDCNT + 1)
HMSEC to (WDCNT + 2) HMSEC, if the sequence is not asserted. There is
an uncertainty of 1 count.
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