參數(shù)資料
型號: MSC1211Y3PAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 32/111頁
文件大小: 1113K
代理商: MSC1211Y3PAGRG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
27
AIN3
AIN4
AIN5
AIN6
AIN0
AIN1
AIN2
AIN7
AINCOM
AGND
Buffer
I
In+
Burnout Detect (2
A)
Burnout Detect (2
A)
Temperature Sensor
80
I
AVDD
In
Figure 13. Input Multiplexer Configuration
ADC INPUT BUFFER
The analog input impedance is always high, regardless of
PGA setting (when the buffer is enabled). With the buffer
enabled, the input voltage range is reduced and the analog
power-supply current is higher. If the limitation of input
voltage range is acceptable, then the buffer is always
preferred. The input impedance of the MSC1211/12/13/14
without the buffer is 7M
/PGA. The buffer is controlled by
the state of the BUF bit in the ADC control register (ADCON0
DCh).
ADC ANALOG INPUT
When the buffer is not selected, the input impedance of the
analog input changes with ACLK clock frequency (ACLK
F6h) and gain (PGA). The relationship is:
Impedance (
W) +
1
f
SAMP @ CS
A
IN Impedance (W) +
1
106
ACLK Frequency
@ 7MW
PGA
where ACLK frequency (f
ACLK) +
f
CLK
ACLK
) 1
and
modclk
+ f
MOD +
f
ACLK
64
.
NOTE: The input impedance for PGA = 128 is the same as
that for PGA = 64 ( that is,
7M
W
64
).
Figure 14 shows the basic input structure of the
MSC1211/12/13/14. The sampling frequency varies
according to the PGA settings, as shown in the table in
Figure 14.
BIPOLAR MODE
UNIPOLAR MODE
PGA
FULL-SCALE RANGE
fSAMP
1
±VREF
+VREF
fMOD
2
±VREF/2
+VREF/2
fMOD
4
±VREF/4
+VREF/4
fMOD
8
±VREF/8
+VREF/8
fMOD S 2
16
±VREF/16
+VREF/16
fMOD S 4
32
±VREF/32
+VREF/32
fMOD S 8
64
±VREF/64
+VREF/64
fMOD S 16
128
±VREF/128
+VREF/128
fMOD S 16
NOTE:
fMOD = ACLK frequency/64
R
SWITCH
(3k typical)
Sampling
Frequency = f
SAMP
High
Impedance
>1G
C
S
AGND
A
IN
(9pF typical)
PGA
C
S
1
9pF
2
18pF
4 to 128
36pF
Figure 14. Analog Input Structure
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