參數(shù)資料
型號(hào)： MSC1211Y3PAGRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 38/111頁(yè)
文件大?。?/td> 1113K
代理商： MSC1211Y3PAGRG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
32
POWER ON RESET
The on-chip Power On Reset (POR) circuitry releases the
device from reset when DVDD ≈ 2.0V. The power supply
ramp rate does not affect the POR. If the power supply falls
below 1.0V for more than 200ms, then the POR will
execute. If the power supply falls below 1.0V for less than
200ms, unexpected operation may occur. If these
conditions are not met, the POR will not execute. For
example, a negative spike on the DVDD supply that does
not remain below 1.0V for at least 200ms, will not initiate
a POR.
If the Analog/Digital Brownout Reset circuit is on, the POR
has no effect.
BROWNOUT RESET
The Brownout Reset (BOR) is enabled through HCR1. If
the conditions for proper POR are not met, or the device
encounters a brownout condition that does not generate a
POR, the BOR can be used to ensure proper device
operation. The BOR will hold the state of the device when
the power supply drops below the threshold level
programmed in HCR1, and then generate a reset when the
supply rises above the threshold level. Note that, as the
device is released from reset and program execution
begins, the device current consumption may increase,
which can result in a power supply voltage drop, which
may initiate another brownout condition.
The BOR level should be chosen to match closely with the
application. That is, with a high external clock frequency,
the BOR level should match the minimum operating
voltage range for the device or improper operation may still
occur.
The BOR voltage is not calibrated until the end of the reset
cycle; therefore, the actual BOR voltage will be
approxiamtely 25% higher than the selected voltage. This
can create a condition where the reset never ends (for
example, when selecting a 4.5V BOR voltage for a 5V
power supply).
IDLE MODE
Idle mode is entered by setting the IDLE bit in the Power
Control register (PCON, 087h). In Idle mode, the CPU,
Timer0, Timer1, and USARTs are stopped, but all other
peripherals and digital pins remain active. The device can
be returned to active mode via an active internal or external
interrupt. This mode is typically used for reducing power
consumption between ADC samples.
By configuring the device prior to entering Idle mode,
further power reductions can be achieved (while in Idle
mode).
These
reductions
include
powering
down
peripherals not in use in the PDCON register (0F1h) and
reducing the system clock frequency by using the System
Clock Divider register (SYSCLK, 0C7h).
STOP MODE
Stop mode is entered by setting the STOP bit in the Power
Control register (PCON, 087h). In STOP mode, all internal
clocks are halted. This mode has the lowest power
consumption. The device can be returned to active mode
only via an external or power-on reset (not brownout
reset).
By configuring the device prior to entering Stop mode,
further power reductions can be achieved (while in Stop
mode). These power reductions include halting the
external clock into the device, configuring all digital I/O
pins as open drain with low output drive, disabling the ADC
buffer, disabling the internal VREF, disabling the DACs, and
setting PDCON to 0FFh to power down all peripherals.
In Stop mode, all digital pins retain their values. If the BOR
is enabled before entering Stop mode, the BOR circuit will
continue to draw approximately 25
A of current from the
power supply during Stop mode. To minimize power
consumption, disable the BOR circuit before entering Stop
mode.
POWER CONSUMPTION CONSIDERATIONS
The
following
suggestions
will
reduce
current
consumption in the MSC1211/12/13/14 devices:
1.
Use the lowest supply voltage that will work in the
application for both AVDD and DVDD.
2.
Use the lowest clock frequency that will work in the
application.
3.
Use Idle mode and the system clock divider
whenever possible. Note that the system clock
divider also affects the ADC clock.
4.
Avoid using 8051-compatible I/O mode on the I/O
ports. The internal pull-up resistors will draw current
when the outputs are low.
5.
Use the delay line for Flash Memory control by
setting the FRCM bit in the FMCON register (SFR
EEh)
6.
Power down peripherals when they are not needed.
Refer to SFR PDCON, LVDCON, ADCON0, and
DACCONx.
For
more
information
about
power
cunsumption
considerations, refer to application report SBAA139,
Minimizing
Power Consumption on the MSC12xx,
available for download at www.ti.com.
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MSC1211Y4PAGR 功能描述:數(shù)據(jù)轉(zhuǎn)換系統(tǒng) Precision ADC & DACs w/8051 CPU & Flash RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
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