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| 型號(hào)： | MR80C52EXXX-25/883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 29/46頁 |
| 文件大?。?/td> | 4720K |
| 代理商： | MR80C52EXXX-25/883 |
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34
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Table 8-2.
Watchdog Timer Configuration
Note:
1. WDTON configuration bit set to “0“ means programmed and “1“ means unprogrammed.
Bit 4 – Res: Reserved Bit
This bit is reserved and will always read as zero.
Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in RSTFLR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF
must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the
failure.
Bits 5, 2:0 – WDP[3:0]: Watchdog Timer Prescaler 3 - 0
The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different
prescaling values and their corresponding time-out periods are shown in Table 8-3 on page 34.
Table 8-3.
Watchdog Timer Prescale Select
WDTON(1)
WDE
WDIE
Mode
Action on Time-out
1
0
Stopped
None
1
0
1
Interrupt
1
0
System Reset
Reset
1
Interrupt and System Reset
Interrupt, then go to System Reset Mode
0
x
System Reset
Reset
WDP3
WDP2
WDP1
WDP0
Number of
WDT Oscillator Cycles
Typical Time-out
at V
CC = 5.0V
0
2K (2048) cycles
16 ms
0
1
4K (4096) cycles
32 ms
0
1
0
8K (8192) cycles
64 ms
0
1
16K (16384) cycles
0.125 s
0
1
0
32K (32768) cycles
0.25 s
0
1
0
1
64K (65536) cycles
0.5 s
0
1
0
128K (131072) cycles
1.0 s
0
1
256K (262144) cycles
2.0 s
1
0
512K (524288) cycles
4.0 s
1
0
1
1024K (1048576) cycles
8.0 s
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