參數(shù)資料
型號(hào): MR80C32-25SBR
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù): 58/80頁(yè)
文件大?。?/td> 5152K
代理商: MR80C32-25SBR
258
XMEGA A [MANUAL]
8077I–AVR–11/2012
In decryption mode, the key is the last subkey of the expanded key defined in the AES standard.
In decryption mode, the key expansion procedure must be executed by software before operation with the AES crypto
module so that the last subkey is ready to be loaded through the KEY register. Alternatively, this procedure can be run in
hardware by using the AES crypto module to process a dummy data block in encryption mode using the same key. After
the end of the encryption, reading from the key memory allows the last subkey to be obtained; i.e., get the result of the
key expansion procedure. Table 23-1 shows the results of reading the key, depending on the mode (encryption or
decryption) and status of the AES crypto module.
Table 23-1. The result of reading the key memory at different stages.
23.4.2 DMA Support
The AES module can trigger a DMA transfer when the encryption/decryption procedure is complete. For more details on
DMA transfer triggers, refer to “Transfer Triggers” on page 52.
Encryption
Decryption
Before data processing
After data processing
Before data processing
After Data Processing
Same key as loaded
The last subkey generated from the
loaded key
Same key as loaded
The initial key generated from the
last loaded subkey
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