參數(shù)資料
型號(hào): MR80C32-25SBR
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 51/80頁
文件大?。?/td> 5152K
代理商: MR80C32-25SBR
251
XMEGA A [MANUAL]
8077I–AVR–11/2012
21.16 Register Summary
21.16.1 Register Summary – USART
21.16.2 Register Summary – USART in SPI Master Mode
21.17 Interrupt Vector Summary
Table 21-11. USART interrupt vectors and their word offset address.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
DATA
DATA[7:0]
+0x01
STATUS
RXCIF
TXCIF
DREIF
FERR
BUFOVF
PERR
RXB8
+0x02
Reserved
+0x03
CTRLA
RXCINTLVL[1:0]
TXCINTLVL[1:0]
DREINTLVL[1:0]
+0x04
CTRLB
RXEN
TXEN
CLK2X
MPCM
TXB8
+0x05
CTRLC
CMODE[1:0]
PMODE[1:0]
SBMODE
CHSIZE[2:0]
+0x06
BAUDCTRLA
BSEL[7:0]
+0x07
BAUDCTRLB
BSCALE[3:0]
BSEL[11:8]
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
+0x00
DATA
DATA[7:0]
+0x01
STATUS
RXCIF
TXCIF
DREIF
+0x02
Reserved
+0x03
CTRLA
RXCINTLVL[1:0]
TXCINTLVL[1:0]
DREINTLVL[1:0]
+0x04
CTRLB
RXEN
TXEN
+0x05
CTRLC
CMODE[1:0]
UDORD
UCPHA
+0x06
BAUDCTRLA
BSEL[7:0]
+0x07
BAUDCTRLB
BSCALE[3:0]
BSEL[11:8]
Offset
Source
Interrupt description
0x00
RXC_vect
USART receive complete interrupt vector
0x02
DRE_vect
USART data register empty interrupt vector
0x04
TXC_vect
USART transmit complete interrupt vector
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