參數(shù)資料
型號： MR80C32-25SBR
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 31/80頁
文件大小： 5152K
代理商： MR80C32-25SBR
222
2466T–AVR–07/10
ATmega16(L)
JTAG Interface
and On-chip
Debug System
Features
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard
Debugger Access to:
– All Internal Peripheral Units
– Internal and External RAM
– The Internal Register File
– Program Counter
– EEPROM and Flash Memories
– Extensive On-chip Debug Support for Break Conditions, Including
–AVR Break Instruction
– Break on Change of Program Memory Flow
– Single Step Break
– Program Memory Breakpoints on Single Address or Address Range
– Data Memory Breakpoints on Single Address or Address Range
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
On-chip Debugging Supported by AVR Studio
Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
Testing PCBs by using the JTAG Boundary-scan capability
Programming the non-volatile memories, Fuses and Lock bits
On-chip Debugging
A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Program-
228, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within ATMEL and to selected third party vendors only.
Figure 112 shows a block diagram of the JTAG interface and the On-chip Debug system. The
TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(Shift Register) between the TDI input and TDO output. The Instruction Register holds JTAG
instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual Data Registers) is used for JTAG Serial Programming via the JTAG interface. The
Internal Scan Chain and Break Point Scan Chain are used for On-chip Debugging only.
Test Access Port –
TAP
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
TMS: Test Mode Select. This pin is used for navigating through the TAP-controller state
machine.
TCK: Test Clock. JTAG operation is synchronous to TCK.
TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data
Register (Scan Chains).
TDO: Test Data Out. Serial output data from Instruction register or Data Register.
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