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參數(shù)資料
| 型號： | MR80C32-20/883:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 49/103頁 |
| 文件大?。?/td> | 25028K |
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142
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
Bit 4:3 – Reserved
These bits are unused and will always read as zero.
Bit 2 – OCF3B: Timer/Counter3, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register B (OCR3B).
Note that a Forced Output Compare (FOC3B) strobe will not set the OCF3B Flag.
OCF3B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF3B can be cleared by writing a logic one to its bit location.
Bit 1 – OCF3A: Timer/Counter3, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT3) value matches the Output
Compare Register A (OCR3A).
Note that a Forced Output Compare (FOC3A) strobe will not set the OCF3A Flag.
OCF3A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF3A can be cleared by writing a logic one to its bit location.
Bit 0 – TOV3: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV3 Flag is set when the timer overflows. Refer to Table 16-5 on page 135 for the TOV3
Flag behavior when using another WGMn3:0 bit setting.
TOV3 is automatically cleared when the Timer/Counter3 Overflow Interrupt Vector is executed.
Alternatively, TOV3 can be cleared by writing a logic one to its bit location.
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