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參數(shù)資料
| 型號(hào)： | MQ80C52TXXX-20:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 26/81頁(yè) |
| 文件大?。?/td> | 663K |
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32
ATtiny28L/V
1062F–AVR–07/06
Register Description
Port A Data Register – PORTA
Port A Control Register –
PACR
Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and always read as zero.
Bit 3 – DDA3: Data Direction PA3
When DDA3 is set (one), the corresponding pin is an output pin. Otherwise, it is an input
pin.
Bit 2 – PA2HC: PORTA2 High Current Enable
When the PA2HC bit is set (one), an additional driver at the output pin PA2 is enabled.
This makes it possible to sink 25 mA at V
CC = 1.8V (VOL = 0.8V). When the PA2HC bit is
cleared (zero), PA2 can sink 15 mA at V
CC = 1.8V (VOL = 0.8V).
Bits 1, 0 – DDA1, DDA0: Data Direction PA1 and PA0
When DDAn is set (one), the corresponding pin is an output pin. Otherwise, it is an input
pin.
Port A Input Pins Address –
PINA
The Port A Input Pins address (PINA) is not a register; this address enables access to
the physical value on each Port A pin. When reading PORTA, the Port A Data Latch is
read and when reading PINA, the logical values present on the pins are read.
Port B Input Pins Address –
PINB
The Port B Input Pins address (PINB) is not a register; this address enables access to
the physical value on each Port B pin. When reading PINB, the logical values present on
the pins are read.
Bit
76543210
$1B
––––
PORTA3
PORTA2
PORTA1
PORTA0
PORTA
Read/Write
RRRR
R/W
Initial Value
00000100
Bit
76543210
$1A
––––
DDA3
PA2HC
DDA1
DDA0
PACR
Read/Write
RRRR
R/W
Initial Value
00000000
Bit
76543210
$19
––––
PINA3
–
PINA1
PINA0
PINA
Read/Write
RRRRRRRR
Initial Value
0000
N/A
0
N/A
Bit
76543210
$16
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
PINB
Read/Write
RRRRRRRR
Initial Value
N/A
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