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參數(shù)資料
| 型號： | MQ80C52TXXX-20:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 24/81頁 |
| 文件大?。?/td> | 663K |
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30
ATtiny28L/V
1062F–AVR–07/06
Figure 26. PORT B Schematic Diagram (Pins PB7 - PB5)
Port D
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.
Three I/O memory address locations are allocated for Port D, one each for the Data
Register – PORTD, $12, Data Direction Register – DDRD, $11 and the Port D Input Pins
– PIND, $10. The Port D Input Pins address is read-only, while the Data Register and
the Data Direction Register are read/write.
The Port D output buffers can sink 10 mA. As inputs, Port D pins that are externally
pulled low will source current if the pull-up resistors are activated.
Port D as General Digital I/O
All eight pins in Port D have equal functionality when used as digital I/O pins.
PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.
If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn
is configured as an input pin. If PDn is set (one) when configured as an input pin, the
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be
cleared (zero), or the pin has to be configured as an output pin. The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Note:
n: 7,6,...,0, pin number
DA
T
A
BUS
PBn
TO LOW-LEVEL DETECTOR
RP:
n:
READ PORT B PIN
5 - 7
RP
MOS
PULL-
UP
PULL-UP PORT B
Table 12. DDDn Bits on Port D Pins
DDDn
PORTDn
I/O
Pull-up
Comment
0
Input
No
Tri-state (high-Z)
0
1
Input
Yes
PDn will source current if ext. pulled low
1
0
Output
No
Push-pull Zero Output
1
Output
NO
Push-pull One Output
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