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參數(shù)資料
| 型號： | MQ80C52TXXX-20:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 11/81頁 |
| 文件大?。?/td> | 663K |
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19
ATtiny28L/V
1062F–AVR–07/06
Register Description
MCU Control and Status
Register – MCUCS
The MCU Control and Status Register contains control and status bits for general MCU
functions.
Bit 7 – PLUPB: Pull-up Enable Port B
When the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins.
When PLUPB is cleared, the pull-ups are disabled. If any of the special functions of Port
B is enabled, the corresponding pull-up(s) is disabled, independent of the value of
PLUPB.
Bit 6 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
Bit 5 – SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to set the Sleep Enable SE bit just before the
execution of the SLEEP instruction.
Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
Mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to “Sleep Modes” below.
Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog reset occurs. The bit is cleared by a Power-on Reset, or by
writing a logical “0” to the flag.
Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
Bit 1 – EXTRF: External Reset Flag
This bit is set if an external reset occurs. The bit is cleared by a Power-on Reset, or by
writing a logical “0” to the flag.
Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is cleared by writing a logical “0” to the
flag.
To make use of the reset flags to identify a reset condition, the user should read and
then clear the flag bits in MCUCS as early as possible in the program. If the register is
cleared before another reset occurs, the source of the reset can be found by examining
the reset flags.
Bit
7
654
32
10
$07
PLUPB
–
SE
SM
WDRF
–
EXTRF
PORF
MCUCS
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
See Bit
Desc.
0
See Bit Description
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| MR80C32-20/883:RD | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
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