10
8111C–MCU Wireless–09/09
AT86RF231
4.
General Circuit Description
This single-chip radio transceiver provides a complete radio transceiver interface between an
antenna and a microcontroller. It comprises the analog radio, digital modulation and demodula-
tion including time and frequency synchronization and data buffering. The number of external
components is minimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and
reception, thus no external antenna switch is needed.
Figure 4-1.
AT86RF231 Block Diagram
The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier
(LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter
(BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital
converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the
digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-
length block coding (spreading) according to
[1] and
[2]. The modulation signal is generated in
the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to
ensure the coherent phase modulation required for demodulation of O-QPSK signals. The fre-
quency-modulated signal is fed to the power amplifier (PA).
A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end.
Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V
supply.
AVREG
LNA
PLL
PA
PPF
BPF
Limiter
ADC
AGC
ext. PA and Power
Control
Configuration Registers
SPI
(Slave)
RSSI
IRQ
CLKM
/RST
SLP_TR
/SEL
MISO
MOSI
SCLK
DIG3/4
RFP
RFN
TX Data
Control Logic
DIG2
Antenna Diversity
FTN, BATMON
XOSC
XT
A
L1
XT
A
L2
Analog Domain
Digital Domain
AES
DIG1/2
AD
DVREG
RX BBP
Frame
Buffer
TX BBP