
3–253
Motorola Sensor Device Data
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*       Multiplier:    MULTP[0..3]
*       Multiplicand:  MULCAN[0..3]
*    Output:
*       Product:       MTEMP[0..3] AND MULCAN[0..3] MTEMP[0] IS THE HIGH
*                          ORDER BYTE AND MULCAN[3] IS THE LOW ORDER BYTE
*
*   THIS ROUTINE DOES NOT USE THE MUL INSTRUCTION FOR THE SAKE OF USERS NOT
*   USING THE HC(7)05 SERIES PROCESSORS.
*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*
*
*
0870 AE 20                      LDX  #32        loop counter
0872 3F 84                      CLR  MTEMP      clean–up for result
0874 3F 85                      CLR  MTEMP+1    *
0876 3F 86                      CLR  MTEMP+2    *
0878 3F 87                      CLR  MTEMP+3    *
087A 36 88                      ROR  MULCAN     low but to carry, the rest one to the right
087C 36 89                      ROR  MULCAN+1   *
087E 36 8A                      ROR  MULCAN+2   *
0880 36 8B                      ROR  MULCAN+3   *
0882 24 18              MNEXT   BCC  ROTATE     if carry is set, do the add
0884 B6 87                      LDA  MTEMP+3    *
0886 BB 83                      ADD  MULTP+3    *
0888 B7 87                      STA  MTEMP+3    *
088A B6 86                      LDA  MTEMP+2    *
088C B9 82                      ADC  MULTP+2    *
088E B7 86                      STA  MTEMP+2    *
0890 B6 85                      LDA  MTEMP+1    *
0892 B9 81                      ADC  MULTP+1    *
0894 B7 85                      STA  MTEMP+1    *
0896 B6 84                      LDA  MTEMP      *
0898 B9 80                      ADC  MULTP      *
089A B7 84                      STA  MTEMP      *
089C 36 84              ROTATE  ROR  MTEMP     else: shift low bit to carry, the rest to the right
089E 36 85                      ROR  MTEMP+1    *
08A0 36 86                      ROR  MTEMP+2    *
08A2 36 87                      ROR  MTEMP+3    *
08A4 36 88                      ROR  MULCAN     *
08A6 36 89                      ROR  MULCAN+1   *
08A8 36 8A                      ROR  MULCAN+2   *
08AA 36 8B                      ROR  MULCAN+3   *
08AC 5A                         DEX             bump the counter down
08AD 26 D3                      BNE  MNEXT      done yet 
08AF 81                         RTS             done
#endasm
08B0 81        RTS                }
void div32()
{
#asm
*
*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*
* Divide 32 bit by 32 bit unsigned integer routine
*
*    Input:
*       Dividend:  DVDND [+0..+3] HIGH ORDER BYTE IS DVND+0
*       Divisor:   DVSOR [+0..+3] HIGH ORDER BYTE IS DVSOR+0
*    Output:
*       Quotient:  QUO [+0..+3]   HIGH ORDER BYTE IS QUO+0
*––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––*
*
08B1 3F 94                      CLR  QUOzero result registers
08B3 3F 95                      CLR  QUO+1      *
08B5 3F 96                      CLR  QUO+2      *
08B7 3F 97                      CLR  QUO+3      *
08B9 A6 01                      LDA  #1         initial loop count
08BB 3D 90                      TST  DVSOR      if the high order bit is set..no need to shift DVSOR
08BD 2B 0F                      BMI  DIV153
*
08BF 4C                 DIV151  INCA            bump the loop counter
08C0 38 93              ASL  DVSOR+3    now shift the divisor until the high order bit = 1
08C2 39 92                      ROL  DVSOR+2
08C4 39 91                      ROL  DVSOR+1    *
08C6 39 90                      ROL  DVSOR      *
08C8 2B 04              BMI  DIV153     done if high order bit = 1
F
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