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參數(shù)資料
| 型號： | MPD800261F1-523-HN2 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC MICROCONTROLLER, PBGA304 |
| 封裝： | 19 X 19 MM, LEAD FREE, PLASTIC, FBGA-304 |
| 文件頁數(shù)： | 27/45頁 |
| 文件大?。?/td> | 369K |
| 代理商： | MPD800261F1-523-HN2 |
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33
Preliminary Data Sheet A17989EE1V0DS00
PD800261
2.4 AC Characteristics
2.4.1 Clock timing
TA = -40 to +85°C, VDDCore = 1.35 V ~ 1.65 V, VDDIO = 3.0 V ~ 3.6 V
Table 2-4: Clock AC Characteristics
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Processor clock frequencyNote 1
PFC
50/100/
150
MHz
Processor clock periodNote 1
PTC
20/10/
6.66
ns
Oscillator clock frequency
PLL_FC
25
- 50 ppm
25
+ 50 ppm
MHz
Reference clock frequency
REF_PLL_FC
25
- 50 ppm
25
+ 50 ppm
MHz
JTAGClk frequency
JTAG_FC
10
MHz
JTAGClk period
JTAG_TC
100
ns
MII transmit clock frequencyNote 2
PHY_Tx_M_FC
2.5
25
MHz
MII transmit clock periodNote 2
PHY_Tx_M_TC
40
400
ns
MII transmit clock input high timeNote 2,3
PHY_Tx_M_TCH
35
65
%
MII transmit clock input low timeNote 2,3
PHY_Tx_M_TCL
35
65
%
MII receive clock frequencyNote 2
PHY_Rx_M_FC
2.5
25
MHz
MII receive clock periodNote 2
PHY_Rx_M_TC
40
400
ns
MII receive clock input high timeNote 2,3
PHY_Rx_M_TCH
35
65
%
MII receive clock input low timeNote 2,3
PHY_Rx_M_TCL
35
65
%
CLK_SDRAM frequency
SDRAM_FC
50
MHz
CLK_SDRAM period
SDRAM_TC
20
ns
CLK_SDRAM clock stability
SDRAM_TCS
+/- 0.2
ns
CLK_SDRAM input high timeNote 2
SDRAM_TCH
40
60
%
CLK_SDRAM input low timeNote 2
SDRAM_TCL
40
60
%
Notes: 1. The actually permitted maximum clock frequency respectively minimum clock period is given by the
CONFIG(4:3) pin setting during reset and depends additionally on the accuracy of the oscillator
clock.
2. MII transmit/receive clock timings are only relevant, if ERTEC 200 is operated in MII mode.
3. High time and low time are specified in per cent of the nominal clock period.
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