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參數(shù)資料
| 型號(hào)： | MPC9774FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大小： | 186K |
| 代理商： | MPC9774FA |
MPC9774
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
231
Driving Transmission Lines
The MPC9774 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20
the drivers can drive
either parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to
Motorola application note AN1091. In most high performance
clock networks point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series
terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of
the line with a 50
resistance to V
CC ÷ 2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9774 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 8 illustrates an output
driving a single series terminated line versus two series
terminated lines in parallel. When taken to its extreme the
fanout of the MPC9774 clock driver is effectively doubled due to
its capability to drive multiple lines.
Figure 8. Single versus Dual Transmission Lines
The waveform plots in Figure 9 show the simulation results
of an output driving a single line versus two lines. In both cases
the drive capability of the MPC9774 output buffer is more than
sufficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta of
only 43 ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the
MPC9774. The output waveform in Figure 9 shows a step in the
waveform, this step is caused by the impedance mismatch seen
looking into the driver. The parallel combination of the 36
series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
VL =VS (Z0 ÷ (RS + R0 + Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 ÷ (18 + 17 + 25)
=1.31 V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.6 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in
this case 4.0 ns).
Figure 9. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 10 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
Figure 10. Optimized Dual Line Termination
14
IN
MPC9774
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC9774
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
TIME (ns)
VOLTAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC9774
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 || 22 = 50 || 50
25
= 25
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9774FAR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC97H73AE | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC97H73AER2 | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC97H73FA | 功能描述:IC PLL CLK GENERATOR 1:12 52LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC97H74AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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