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參數(shù)資料
| 型號： | MPC9774FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 186K |
| 代理商： | MPC9774FA |
MPC9774
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
229
APPLICATIONS INFORMATION
MPC9774 Configurations
Configuring the MPC9774 amounts to properly configuring
the internal dividers to produce the desired output frequencies.
The output frequency can be represented by this formula:
where fREF is the reference frequency of the selected input
clock source (CCLK0 or CCLK1), M is the PLL feedback divider
and N is a output divider. M is configured by the FSEL_FB[0:1]
and N is individually configured for each output bank by the
FSEL_A, FSEL_B and FSEL_C inputs.
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 500 MHz in order to achieve stable
PLL operation:
fVCO,MIN ≤ (fREF VCO_SEL M) ≤ fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-two or
a divide-by-four and can be used to situate the VCO into the
specified frequency range. This divider is controlled by the
VCO_SEL pin. VCO_SEL effectively extends the usable input
frequency range while it has no effect on the output to reference
frequency ratio. The output frequency for each bank can be
derived from the VCO frequency and output divider:
fQA[4:0] = fVCO ÷ (VCO_SEL NA)
fQB[4:0] = fVCO ÷ (VCO_SEL NB)
fQC[3:0] = fVCO ÷ (VCO_SEL NC)
Table 9 shows the various PLL feedback and output dividers.
The output dividers for the three output banks allow the user to
configure the outputs into 1:1, 2:1, 3:2, and 3:2:1 frequency
the MPC9774.
Figure 3. Example Configuration
Figure 4. Example Configuration
÷ VCO_SEL
÷ M
÷ N
fREF
fOUT
fOUT = fREF M ÷ N
PLL
Table 9. MPC9774 Divider
Divider
Function
VCO_SEL
Values
M
PLL Feedback
FSEL_FB[0:1]
÷ 2
8, 12, 16, 24
÷ 4
16, 24, 32, 48
NA
Bank A Output
Divider FSEL_A
÷ 24, 8
÷ 48, 16
NB
Bank B Output
Divider FSEL_B
÷ 24, 8
÷ 48, 16
NC
Bank C Output
Divider FSEL_C
÷ 28, 12
÷ 4
16, 24
MPC9774
fREF = 20.83 MHz
125 MHz
62.5 MHz
20.83 MHz (Feedback)
62.5 MHz
CCLK0
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
CCLK1
CCLK_SEL
FB_IN
0
1
0
11
0
MPC9774 example configuration (feedback of
QFB = 20.83 MHz, VCO_SEL =
÷ 2, M = 12,
NA = 2, NB = 4, NC = 4, fVCO = 500 MHz).
Frequency Range
Min
Max
Input
8.33 MHz
20.83 MHz
QA outputs
50 MHz
125 MHz
QB outputs
25 MHz
62.5 MHz
QC outputs
25 MHz
62.5 MHz
MPC9774
fREF = 25 MHz
100 MHz
50 MHz
25 MHz (Feedback)
33.3 MHz
CCLK0
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
CCLK1
CCLK_SEL
FB_IN
0
1
01
0
MPC9774 example configuration (feedback of
QFB = 25 MHz, VCO_SEL =
÷ 2, M = 8, N
A = 2,
NB = 4, NC = 6, fVCO = 400 MHz).
Frequency Range
Min
Max
Input
20 MHz
48 MHz
QA outputs
50 MHz
120 MHz
QB outputs
50 MHz
120 MHz
QC outputs
100 MHz
200 MHz
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