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參數(shù)資料
| 型號： | MPC9774FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大小： | 186K |
| 代理商： | MPC9774FA |
MPC9774
230
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Using the MPC9774 in Zero-Delay Applications
Nested clock trees are typical applications for the MPC9774.
Designs using the MPC9774 as LVCMOS PLL fanout buffer
with zero insertion delay will show significantly lower clock skew
than clock distributions developed from CMOS fanout buffers.
The external feedback of the MPC9774 clock driver allows for
its use as a zero delay buffer. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a near
zero delay through the device (the propagation delay through
the device is virtually eliminated). The maximum insertion delay
of the device in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or long-term
jitter), feedback path delay and the output-to-output skew error
relative to the feedback output.
Calculation of Part-to-Part Skew
The MPC9774 zero delay buffer supports applications where
critical clock signal timing can be maintained across several
devices. If the reference clock inputs of two or more MPC9774
are connected together, the maximum overall timing uncertainty
from the common CCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 5. MPC9774 Maximum Device-to-Device Skew
Due to the statistical nature of I/O jitter a RMS value (1
σ) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 10.
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device.
Due to the frequency dependence of the static phase offset
I/O jitter and the specified t() parameter relative to the input
reference frequency results in a precise timing performance
analysis.
In the following example calculation a I/O jitter confidence
factor of 99.7% (
± 3σ) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of –470 ps to +320 ps relative to CCLK (PLL
feedback =
÷ 8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 15 ps RMS max., static phase
offset t() = –250 ps to +100 ps):
tSK(PP) = [–250 ps...+100 ps] + [-175 ps...175 ps] +
[(15 ps –3)...(15 ps 3)] + tPD, LINE(FB)
tSK(PP) = [–470 ps...+320 ps] + tPD, LINE(FB)
Figure 6. MPC9774 I/O Jitter
Figure 7. MPC9774 I/O Jitter
tPD,LINE(FB)
tJIT()
±tSK(O)
–t()
+t()
tJIT()
±tSK(O)
tSK(PP)
Max. skew
CCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Table 10. Confidence Factor CF
CF
Probability of Clock Edge within the Distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
VCO Frequency [MHz]
200
250
300
350
400
450
500
100
80
60
40
20
0
FB =
÷ 8
FB =
÷ 32
FB =
÷ 16
Maximum I/O Phase Jitter (RMS) versus Frequency Parameter:
PLL Feedback Divider FB
t jit[
φ]
[p
s]
RM
S
t jit[
φ]
[p
s]
RMS
VCO Frequency [MHz]
200
250
300
350
400
450
500
120
100
80
60
40
20
0
FB =
÷ 12
FB =
÷ 24
Maximum I/O Phase Jitter (RMS) versus Frequency Parameter:
PLL Feedback Divider FB
FB =
÷ 48
160
140
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9774FAR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC97H73AE | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC97H73AER2 | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC97H73FA | 功能描述:IC PLL CLK GENERATOR 1:12 52LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC97H74AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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