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| 型號： | MPC9608ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 315K |
| 代理商： | MPC9608ACR2 |
Advanced Clock Drivers Device Data
Freescale Semiconductor
3
MPC9608
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
PLL reference clock signal
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to a QFB output
F_RANGE[0:1]
Input
LVCMOS
PLL frequency range select
BSEL
Input
LVCMOS
Frequency divider select for bank B outputs
PLL_EN
Input
LVCMOS
PLL enable/disable
OE
Input
LVCMOS
Output enable/disable (high-impedance tristate)
CLK_STOP
Input
LVCMOS
Synchronous clock enable/stop
QA0-4, QB0-4
Output
LVCMOS
Clock outputs
QFB
Output
LVCMOS
PLL feedback signal output. Connect to FB_IN
GND
Supply
Ground
Negative power supply
VCCA
Supply
VCC
PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter
for the analog power supply pin VCCA. Refer to the Applications Information section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
Table 2. Function Table
Control
Default
0
1
F_RANGE[0:1]
00
PLL frequency range. Refer to Table 3. Clock Frequency Configuration for QFB Connected to FB_INT
BSEL
0
fQB0-4 = fQA0-4
fQB0-4 = fQA0-4 ÷ 2
CLK_STOP
0
Outputs enabled
Outputs synchronously stopped in logic low state
OE
0
Outputs enabled (active)
Outputs disabled (high-impedance state), independent on
CLK_STOP. Applying OE = 1 and PLL_EN = 1 resets the device.
The PLL feedback output QFB is not affected by OE.
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is substituted for the internal
VCO output. MPC9608 is fully static and no minimum frequency
limit applies. All PLL related AC characteristics are not applicable.
Applying OE = 1 and PLL_EN = 1 resets the device.
Table 3. Clock Frequency Configuration for QFB Connected to FB_IN
F_RANGE[0]
F_RANGE[1]
BSEL
fREF (CCLK)
range [MHz]
QA0-QA4
QB0-B4
QFB
Ratio
fQA0-4 [MHz]
Ratio
fQB0-4 [MHz]
0
100.0 – 200.0
fREF
100.0 – 200.0
fREF
100.0 – 200.0
fREF
00
1
fREF ÷ 250.0 – 25.0
fREF
0
1
0
50.0 – 100.0
fREF
50.0 – 100.0
fREF
50.0 – 100.0
fREF
01
1
fREF ÷ 225.0 – 50.0
fREF
1
0
25.0 – 50.0
fREF
25.0 – 50.0
fREF
25.0 – 50.0
fREF
10
1
fREF ÷ 212.5 – 25.0
fREF
1
0
12.5 – 25.0
fREF
12.5 – 25
fREF
12.5 – 25.0
fREF
11
1
fREF ÷ 26.25 – 12.5
fREF
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