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參數(shù)資料
| 型號： | MPC930FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 326K |
| 代理商： | MPC930FA |
MPC930 MPC931
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
58
schemes discussed in this section should be adequate to elim-
inate power supply noise related problems in most designs.
Using the Power Management Features of the
MPC930/931
The MPC930/931 clock driver offers two different features
that designers can take advantage of for managing power dis-
sipation in their designs. The first feature allows the user to
turn off outputs which drive portions of the system which may
go idle in a sleep mode. The Shut_Dn pins allow for three dif-
ferent combinations of output shut down schemes. The
schemes are summarized in the function tables in the data
sheet. The MPC930/931 synchronizes the shut down signals
internal to the chip and applies them in a manner which elimi-
nates the possibility of creating runt pulse on the outputs. The
device waits for the output to go into the “LOW” state prior to
disabling. When the outputs are re–enabled the device waits
and re–enables the output such that the transition is synchro-
nous and in the proper phase relationship to the outputs which
remained active.
The Power_Dn pin offers another means of implementing
power management schemes into a design. To use this feature
the device must be set up in its normal operating mode with the
Power_Dn pin “LOW”, in addition the user must use the inter-
nal feedback option. If the external feedback option were used
the output frequency reduction would change the feedback fre-
quency and the PLL will lose lock. When the Power_Dn pin is
driven “HIGH” the MPC930/931 synchronizes the signal to the
internal clock and then seemlessly reduces the frequency of
the outputs by one half. The Power_Dn signal is synchronized
to the slowest internal VCO clock. It waits until both VCO
clocks are in the “LOW” state and then switches from the nomi-
nal speed VCO clock to the half speed VCO clock. This will in
turn cause the current output pulse to stretch to reflect the re-
duction in output frequency. When the Power_Dn pin is
brought back “LOW” the device will again wait until both of the
VCO clocks are “LOW” and then switch to the nominal VCO
clock. This will cause the current output pulses, and all succes-
sive pulses, to shrink to match the higher output frequency.
Both the power up and power down features are illustrated in
the timing diagrams of in this data sheet.
Timing diagrams for both of the power management fea-
tures are shown in Figure 3 and Figure 4 on page 51.
Using the On–Board Crystal Oscillator
The MPC930 features an on–board crystal oscillator to al-
low for seed clock generation as well as final distribution. The
on–board oscillator is completely self contained so that the
only external component required is the crystal. As the oscilla-
tor is somewhat sensitive to loading on its inputs the user is
advised to mount the crystal as close to the MPC930/931 as
possible to avoid any board level parasitics. To facilitate co–
location surface mount crystals are recommended, but not re-
quired.
The oscillator circuit is a series resonant circuit as opposed
to the more common parallel resonant circuit, this eliminates
the need for large on–board capacitors. Because the design is
a series resonant design for the optimum frequency accuracy
a series resonant crystal should be used (see specification
table below). Unfortunately most off the shelf crystals are char-
acterized in a parallel resonant mode. However a parallel reso-
nant crystal is physically no different than a series resonant
crystal, a parallel resonant crystal is simply a crystal which has
been characterized in its parallel resonant mode. Therefore in
the majority of cases a parallel specified crystal can be used
with the MPC930 with just a minor frequency error due to the
actual series resonant frequency of the parallel resonant spe-
cified crystal. Typically a parallel specified crystal used in a
series resonant mode will exhibit an oscillatory frequency a
few hundred ppm lower than the specified value. For most
processor implement– ations a few hundred ppm translates
into kHz inaccuracies, a level which does not represent a ma-
jor issue.
Table 4. Crystal Specifications
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75ppm at 25°C
Frequency/Temperature Stability
±150pm 0 to 70°C
Operating Range
0 to 70
°C
Shunt Capacitance
5–7pF
Equivalent Series Resistance (ESR)
50 to 80
Max
Correlation Drive Level
100
W
Aging
5ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant discus-
sion.
The MPC930 is a clock driver which was designed to gener-
ate outputs with programmable frequency relationships and
not a synthesizer with a fixed input frequency. As a result the
crystal input frequency is a function of the desired output fre-
quency. For a design which utilizes the external feedback to
the PLL the selection of the crystal frequency is straight for-
ward; simply chose a crystal which is equal in frequency to the
fed back signal. To determine the crystal required to produce
the desired output frequency for an application which utilizes
internal feedback the block diagram of Figure 15 should be
used. The P and the M values for the MPC930/931 are also
included in Figure 15. The M values can be found in the config-
uration tables included in this applications section.
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相關代理商/技術參數(shù) |
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| MPC931 | 制造商:Motorola Inc 功能描述: |
| MPC9315 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:2.5V and 3.3V CMOS PLL Clock Generator and Driver |
| MPC9315AC | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315ACR2 | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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