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參數(shù)資料
| 型號(hào)： | MPC930FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 326K |
| 代理商： | MPC930FA |
MPC930 MPC931
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
57
outputs are switching at the same frequency there is no edge
dis p lac e ment and the jitter is reduc ed to that of
the PLL.
Figure 12 graphically represents the PLL jitter of the
MPC930/931. The data was taken for several different output
configurations. Because of the relatively few outputs on the
MPC930/931, the multimodal distribution is of a second order
affect on the 930/931 and can be ignored. As one can see in
the figure the PLL jitter is much less dependent on output con-
figuration than on internal VCO frequency. However, for a giv-
en VCO frequency, a lower output frequency produces more
jitter.
Figure 12. RMS Jitter versus VCO Frequency
(Qa0 Output)
10
15
20
25
30
35
40
45
80
120
160
200
240
280
Conf 1
Conf 2
Conf 1 = Qa=÷2, Qb=Qc=÷4
Conf 2 = Qa=÷2, Qb=Qc=Shut Down
Conf 3 = Qa=÷4, Qb=Qc=Shut Down
VCO Frequency (MHz)
RMS
Jitter
(ps)
Figure 13. RMS Jitter versus Output Frequency
(Qa0 Output)
10
15
20
25
30
35
20
40
60
80
100
120
140
Frequency Output (MHz)
RMS
Jitter
(ps)
Conf 2 = Qa=÷2, Qb=Qc=Shut Down
Conf 3 = Qa=÷4, Qb=Qc=Shut Down
Conf 3
Conf 2
Conf 3
Finally from the data there are some general guidelines that,
if followed, will minimize the output jitter of the device. First and
foremost always configure the device such that the VCO runs
as fast as possible. This is by far the most critical parameter in
minimizing jitter. Second keep the reference frequency as high
as possible. More frequent updates at the phase detector will
help to reduce jitter. Note that if there is a tradeoff between
higher reference frequencies and higher VCO frequency al-
ways chose the higher VCO frequency to minimize jitter. The
third guideline is to try to shut down outputs that are unused.
Minimizing the number of switching outputs will minimize out-
put jitter.
Power Supply Filtering
The MPC930/931 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally sus-
ceptible to random noise, especially if this noise is seen on the
power supply pins. The MPC930/931 provides separate power
supplies for the output buffers (VCCO) and the internal PLL
(PLL_VCC) of the device. The purpose of this design tech-
nique is to try and isolate the high switching noise digital out-
puts from the relatively sensitive internal analog phase–locked
loop. In a controlled environment such as an evaluation board
this level of isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
PLL_VCC pin for the MPC930/931.
Figure 14. Power Supply Filter
PLL_VCC
VCC
MPC930/931
0.01F
22F
0.01F
3.3V
RS=10-15
Figure 14 illustrates a typical power supply filter scheme.
The MPC930/931 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter should
be designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that will
be seen between the VCC supply and the PLL_VCC pin of the
MPC930/931. From the data sheet the IPLL_VCC current (the
current sourced through the PLL_VCC pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the PLL_VCC pin very little DC voltage drop can
be tolerated when a 3.3V VCC supply is used. The resistor
shown in Figure 14 must have a resistance of 10–15
to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for noise
whose spectral content is above 20KHz. As the noise frequen-
cy crosses the series resonant point of an individual capacitor
it’s overall impedance begins to look inductive and thus in-
creases with increasing frequency. The parallel capacitor com-
bination shown ensures that a low impedance path to ground
exists for frequencies well above the bandwidth of the PLL.
Although the MPC930/931 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded
due to system power supply noise. The power supply filter
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MPC931 | 制造商:Motorola Inc 功能描述: |
| MPC9315 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:2.5V and 3.3V CMOS PLL Clock Generator and Driver |
| MPC9315AC | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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