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參數(shù)資料
| 型號(hào)： | MPC930FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
| 封裝： | TQFP-32 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 326K |
| 代理商： | MPC930FA |
MPC930 MPC931
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
55
MPC930
Figure 5. Dual Frequency Configuration
Div_Sela
`0'
Div_Selb
`1'
Div_Selc
`0'
ExtFB_Sel
`0'
Input Ref
16.66MHz
66.66MHz (Processor)
Qa
33.33MHz (PCI)
Qb
33.33MHz (PCI)
Qc
2
MPC930
Figure 6. Single Frequency Configuration
Div_Sela
`1'
Div_Selb
`1'
Div_Selc
`0'
ExtFB_Sel
`0'
Input Ref
16.66MHz
33.33MHz
Qa
33.33MHz
Qb
33.33MHz
Qc
2
MPC931
Figure 7. “Zero” Delay Fractional Multiplier
Div_Sela
`1'
Div_Selb
`1'
Div_Selc
`1'
ExtFB_Sel
`1'
Input Ref
33.33MHz
50MHz
Qa
50MHz
Qb
33.33MHz
Qc
2
Figure 8. “Zero” Delay Fractional Divider
Ext_FB
1
MPC931
Div_Sela
`0'
Div_Selb
`1'
Div_Selc
`1'
ExtFB_Sel
`1'
Input Ref
50MHz
100MHz
Qa
50MHz
Qb
33.33MHz
Qc
2
Ext_FB
1
MPC931
Figure 9. “Zero” Delay Multiply by 3 (50% Duty Cycle)
Div_Sela
`0'
Div_Selb
`0'
Div_Selc
`1'
ExtFB_Sel
`1'
Input Ref
33.33MHz
100MHz
Qa
100MHz
Qb
33.33MHz
Qc
2
Figure 10. “Zero” Delay Divide by 3 (50% Duty Cycle)
Ext_FB
1
MPC931
Div_Sela
`0'
Div_Selb
`0'
Div_Selc
`1'
ExtFB_Sel
`1'
Input Ref
100MHz
Qa
100MHz
Qb
33.33MHz
Qc
2
Ext_FB
1
Using the MPC930/931 as a Zero Delay Buffer
The external feedback option of the MPC930/931 clock driv-
er allows for its use as a zero delay buffer. By using one of the
outputs as a feedback to the PLL the propagation delay
through the device is eliminated. The PLL works to align the
output edge with the input reference edge thus producing a
near zero delay. The Tpd of the device is specified in the speci-
fication tables. For zero delay buffer applications, the MPC931
is recommended over the MPC930. The MPC931 has been
optimized and specified specifically for use as a zero delay
buffer.
When used as a zero delay buffer the MPC930/931 will like-
ly be in a nested clock tree application. For these applications
the MPC931 offers a LVPECL clock input as a PLL reference.
This allows the user to use LVPECL as the primary clock dis-
tribution device to take advantage of its far superior skew per-
formance. The MPC931 then can lock onto the LVPECL refer-
ence and translate with near zero delay to low skew LVCMOS
outputs. Clock trees implemented in this fashion will show sig-
nificantly tighter skews than trees developed from CMOS fan-
out buffers.
To minimize part–to–part skew the external feedback option
again should be used. The PLL in the MPC931 decouples the
delay of the device from the propagation delay variations of the
internal gates. From the specification table one sees a Tpd
variation of only
±150ps, thus for multiple devices under identi-
cal configurations the part–to–part skew will be around 850ps
(300ps for Tpd variation plus 300ps output–to–output skew
plus 250ps jitter). For devices that are configured differently
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC931 | 制造商:Motorola Inc 功能描述: |
| MPC9315 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:2.5V and 3.3V CMOS PLL Clock Generator and Driver |
| MPC9315AC | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-8 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9315FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類(lèi)型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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