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參數(shù)資料
| 型號： | MPC92433AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/21頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER LVPECL 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 1.428GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC92433 Data Sheet
1428MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
MPC92433 REVISION 3 FEBRUARY 6, 2013
13
2013 Integrated Device Technology, Inc.
LOCK Detect
The LOCK detect circuitry indicates the frequency-lock status
of the PLL by setting and resetting the pin LOCK and register bit
LOCK simultaneously. After acquiring an internal frequency lock
state, the assertion of the LOCK signal is delayed at least 256
reference clock cycles to prevent signaling temporary PLL locks
during frequency transitions. The LOCK signal is deasserted
when the PLL lost lock, for instance when the reference clock is
removed: the LOCK signal goes low after missing at least two fref
clock cycles (NREF(UNLOCK)). The PLL may also lose lock when
the PLL feedback-divider M or pre-divider P is changed or the
DEC/INC command is issued. The PLL may not lose lock as a
result of slow reference frequency changes. In any case of losing
LOCK, the PLL attempts to re-lock to the reference frequency.
Output Clock Stop
Asserting CLK_STOPx will stop the respective output clock in
logic low state. The CLK_STOPx control is internally
synchronized to the output clock signal, therefore, enabling
and disabling outputs does not produce runt pulses. See
Figure 5.The clock stop controls of the QA and QB outputs are
independent on each other. If the QB runs at half of the QA output
frequency and both outputs are enabled at the same time, the first
clock pulse of QA may not appear at the same time of the first QB
output. (See Figure 6.) Concident rising edges of QA and QB stay
synchronous after the assertion and de-assertion of the
CLK_STOPx controls. Asserting MR always resets the output
divider to a logic low output state, with the risk of producing an
output runt pulse.
Figure 5. Clock Stop Timing for NB = 0 (fQA = fQB)
Figure 6. Clock Stop Timing for NB = 1 (fQA = 2 fQB)
CLK_STOPx
Qx
(Disable)
(Enable)
tP_DIS
tP_EN
CLK_STOPA,B
QA
QB
(Disable)
(Enable)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439EI | 功能描述:時鐘合成器/抖動清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439EIR2 | 功能描述:時鐘合成器/抖動清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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