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參數(shù)資料
| 型號： | MPC92433AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 48-LQFP |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 1.428GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC92433 Data Sheet
1428MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
MPC92433 REVISION 3 FEBRUARY 6, 2013
12
2013 Integrated Device Technology, Inc.
Read Mode (R/W = 1)
The configuration registers are read by the bus controller by the
initiation of a read transfer. The MPC92433 supports read
transfers immediately after the first byte without a change in the
transfer direction. Immediately after the bus controller sends the
slave address, the MPC92433 acknowledges and then sends
both configuration register PLL_L and PLL_H (back-to-back) to
the bus controller. The CMD register cannot be read. In order to
read the two synthesizer registers and the current PLL
configuration setting, the user can 1) read PLL_L, PLL_H, write
the GET command (loads the current configuration into PLL_L,
PLL_H) and read PLL_L, PLL_H again. Note that the PLL_L,
PLL_H registers and divider settings may not be equivalent after
the following cases:
a.
Writing the INC command
b.
Writing the DEC command
c.
Writing PLL_L, PLL_H registers with a new
configuration and not writing the LOAD command.
Device Startup
General Device Configuration
It is recommended to reset the MPC92433 during or
immediately after the system powers up (MR = 0). The device
acquires an initial PLL divider configuration through the parallel
interface pins M[9:0], NA[2:0], N, and P(1) with the low-to-high
transition of MR(2). PLL frequency lock is achieved within the
specified lock time (tLOCK) and is indicated by an assertion of the
LOCK signal which completes the startup procedure. It is
recommended to disable the outputs (CLK_STOPx = 0) until PLL
lock is achieved to suppress output frequency transitions. The
output frequency can be reconfigured at any time through either
the parallel or the serial interface.
Note that a PLL configuration obtained by the parallel interface
can be read through I2C independent on the current programming
mode (parallel or serial). Refer to the I2C — Register Access in
Parallel Mode section for additional information on how to read a
PLL startup configuration through the I2C interface.
Starting-Up Using the Parallel Interface
The simplest way to use the MPC92433 is through the parallel
interface. The serial interface pins (SDA, SDL) and ADDR[1:0])
can be left open and PLOAD is set to logic low. After the release
of MR and at any other time the PLL/output frequency
configuration is directly set to through the M[9:0], NA[2:0], NB, and
P pins.
Start-Up Using the Serial (I2C) Interface
Figure 4. Start-Up Using I2C Interface
Set PLOAD = 1, CLK_STOPx = L and leave the parallel
interface pins (M[9:0], NA[2:0], N, and P) open. The PLL dividers
are configured by the default configuration at the low-to-high
transition of MR. This initial PLL configuration can be re-
programmed to the final VCO frequency at any time through the
serial interface. After the PLL achieved lock at the desired VCO
frequency, enable the outputs by setting CLK_STOPx = H. PLL
lock and re-lock (after any configuration change through M or P)
is indicated by LOCK being asserted.
Table 19. Configuration Register Read Transfer
1 bit
7 bits
1 bit
8 bits
1 bit
8 bits
1 bit
Start
Slave address
R/W
ACK
PLL_L
ACK
PLL_H
ACK
Stop
10110xx(1)
1. xx = state of ADR1, ADR0 pins
1
Data
Master
Mast
Slave
Mast
Slave
Master
Slave
1. The parallel interface pins M[9:0], NA[2:0], N, and P may be left open (floating). In this case the initial PLL configuration will have the default setting of
M = 500, P = 1, NA[2:0] = 010, NB = 0, resulting in an internal VCO frequency of 2000 MHz (fref = 16 MHz) and an output frequency of 250 MHz.
2. The initial PLL configuration is independent on the selected programming mode (PLOAD low or high)
VCC
MR
P, M, N
PLOAD
LOCK
CLK_STOPx
QA, QB
Stable & Valid
Selects I2C
Acquiring Lock
PLL Lock
Disabled (Low)
tPLH
Active
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439EI | 功能描述:時鐘合成器/抖動清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439EIR2 | 功能描述:時鐘合成器/抖動清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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