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參數(shù)資料
| 型號(hào)： | MPC92433AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 3/21頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER LVPECL 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類(lèi)型： | 時(shí)鐘/頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 1.428GHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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MPC92433 Data Sheet
1428MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
MPC92433 REVISION 3 FEBRUARY 6, 2013
11
2013 Integrated Device Technology, Inc.
I2C — Register Access in Parallel Mode
The MPC92433 supports the configuration of the synthesizer
through the parallel interlace (PLOAD = 0) and serial interface
(PLOAD = 1). Register contents and the divider configurations are
not changed when the user switches from parallel mode to serial
mode. However, when switching from serial mode to parallel
mode, the PLL dividers immediately reflect the logical state of the
hardware pins M[9:0], NA[2:0], NB, and P.
Applications using the parallel interface to obtain a PLL
configuration can use the serial interface to verify the divider
settings. In parallel mode (PLOAD = 0), the MPC92433 allows
read-access to PLL_L and PLL_H through I2C (if PLOAD = 0, the
current PLL configuration is stored in PLL_L, PLL_H. The GET
command is not necessary and also not supported in parallel
mode). After changing from parallel to serial mode (PLOAD =1),
the last PLL configuration is still stored in PLL_L, PLL_H. The user
now has full write and read access to both configuration registers
through the I2C bus and can change the configuration at any time.
Programming the I2C Interface
The 7-bit I2C slave address of the MPC92433 synthesizer is a
combination of a 5-bit fixed addresses and two variable bits which
are set by the hardware pins ADR[1:0]. Bit 0 of the MPC92433
slave address is used by the bus controller to select either the
read or write mode. ’0’ indicates a transmission (I2C-WRITE) to
the MPC92433. ’1’ indicates a request for data (I2C-READ) from
the synthesizer. The hardware pins ADR1 and ADR0 and should
be individually set by the user to avoid address conflicts of multiple
MPC92433 devices on the same I2C bus.
Write Mode (R/W = 0)
The configuration registers are written by the bus controller by
the initiation of a write transfer with the MPC92433 slave address
(first byte), followed by the address of the configuration register
(second byte: 0x00, 0x01 or 0xF0), and the configuration data
byte (third byte). This transfer may be followed by writing more
registers by sending the configuration register address followed
by one data byte. Each byte sent by the bus controller is
acknowledged by the MPC92433. The transfer ends by a stop bit
sent by the bus controller. The number of configuration data bytes
and the write sequence are not restricted.
Table 15. CMD (0xF0): PLL Command (Write-Only)
Command
Op-Code
Description
INC
xxxx0001b
(0x01)
Increase internal PLL frequency
M:=M+1
DEC
xxxx0010b
(0x02)
Decrease internal PLL frequency
M:=M-1
LOAD
xxxx0100b
(0x04)
Update the PLL divider config.
PLL divider M, N, P:=PLL_L, PLL_H
GET
xxxx1000b
(0x08)
Update the configuration registers
PLL_L, PLL_H:=PLL divider M, N, P
Table 16. PLL Configuration in Parallel and Serial Modes
PLL
Configuration
Parallel
Serial (Registers
PLL_L, PLL_H)
M[9:0]
Set pins M9–M0
M[9:0] (R/W)
NA[2:0]
Set pins NA2...NA0
NA[2:0] (R/W)
NB
Set pin NB
NB (R/W)
P
Set pin P
P (R/W)
LOCK status
LOCK pin 26
LOCK (Read only)
Table 17. I2C Slave Address
Bit
76
5
4
3
2
1
0
Value
10
1
0
Pin
ADR1
Pin
ADR0
R/W
Table 18. Complete Configuration Register Write Transfer
1 bit
7 bits
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
8 bits
1 bit
Start
Slave address
R/W
ACK
&PLL_H
ACK
Config-Byte 1
ACK
&PLL_L
ACK
Config-Byte 2
ACK
Stop
10110xx(1)
1. xx = state of ADR1, ADR0 pins
0
0x01
Data
0x00
Data
Master
Mast
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Mast
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92439 | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱(chēng):844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱(chēng):844S012AKI-01LFT |
| MPC92439EI | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439EIR2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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