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參數(shù)資料
| 型號(hào)： | MPC92432AE |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 1360 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | ROHS COMPLIANT, LQFP-48 |
| 文件頁(yè)數(shù)： | 18/19頁(yè) |
| 文件大小： | 611K |
| 代理商： | MPC92432AE |
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Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC92432
APPLICATION INFORMATION
Output Frequency Configuration
The MPC92432 is a programmable frequency source
(synthesizer) and supports an output frequency range of
21.25 – 1360 MHz. The output frequency fOUT is a function of
the reference frequency fREF and the three internal PLL
dividers P, M, and N. fOUT can be represented by this formula:
fOUT = (fREF ÷ P) M ÷ (NA, B)(1)
The M, N and P dividers require a configuration by the user
to achieve the desired output frequency. The output divider,
NA, determines the achievable output frequency range (see
Table 7). The PLL feedback-divider M is the frequency
multiplication factor and the main variable for frequency
synthesis. For a given reference frequency fREF, the PLL
feedback-divider M must be configured to match the
specified VCO frequency range in order to achieve a valid
PLL configuration:
fVCO = (fREF ÷ P) M and
(2)
1360
≤ fVCO ≤ 2720
(3)
The output frequency may be changed at any time by
changing the value of the PLL feedback divider M. The
smallest possible output frequency change is the synthesizer
granularity G (difference in fOUT when incrementing or
decrementing M). At a given reference frequency, G is a
function of the PLL pre-divider P and post-divider N:
G = fREF ÷ (P NA,B)(4)
The NB divider configuration determines if the output QB
generates a 1:1 or 2:1 frequency copy of the QA output signal.
The purpose of the PLL pre-divider P is to situated the PLL
into the specified VCO frequency range fVCO (in combination
with M). For a given output frequency, P = 4 results in a
smaller output frequency granularity G, P = 2 results a larger
output frequency granularity G and also increases the PLL
bandwidth compared to the P = 2 setting.
The following example illustrates the output frequency
range of the MPC92432 using a 16-MHz reference
frequency.
Example Output Frequency Configuration
If a reference frequency of 16 MHz is available, an output
frequency at QA of 250 MHz and a small frequency
granularity is desired, the following steps would be taken to
identify the appropriate P, M, and N configuration:
1.
Use Table 7 to select the output divider, NA, that
matches the desired output frequency or frequency
range. According to Table 7, a target output frequency
of 250 MHz falls in the fOUT range of 170 to 340 MHz
and requires to set NA = 8.
2.
Calculate the VCO frequency fVCO = fOUT NA, which is
2000 MHz in this example.
3.
Determine the PLL feedback divider: M = fVCO ÷P.
The smallest possible output granularity in this example
calculation is 500 kHz (set P = 4). M calculates to a
value of 2000 ÷ 4 = 500.
4.
Configure the MPC92432 with the obtained settings:
M[9:0] = 0111110100b (binary number for M=500)
NA[2:0] = 010
(÷8 divider, see Table 9)
P = 1
(÷4 divider, see Table 8)
NB = 0
(fOUT, QB = fOUT, QA)
5.
Use either parallel or serial interface to apply the
setting. The I2C configuration byte for this examples
are:
PLL_H=01010010b and PLL_L=11110100b.
See Table 14 and Table 15 for register maps.
PLL Divider Configuration
Table 7. Frequency Ranges (fREF = 16 MHz)
fOUT (QA) [MHz]
NA
M
P
G [MHz]
680 – 1360
NA = 2
170 – 340
2
4
340 – 680
4
2
340 – 680
NA = 4
170 – 340
2
340 – 680
4
1
170 – 340
NA = 8
170 – 340
2
1
340 – 680
4
0.5
85 – 170
NA = 16
170 – 340
2
0.5
340 – 680
4
0.25
42.5 – 85
NA = 32
170 – 340
2
0.25
340 – 680
4
0.125
21.25 – 42.5
NA = 64
170 – 340
2
0.125
340 – 680
4
0.0625
Table 8. Pre-PLL Divider P
PValue
0fREF ÷ 2
1fREF ÷ 4
Table 9. Post-PLL Divider NA
NA0
NA1
NA2
fOUT (QA)
000
fVCO ÷ 2
001
fVCO ÷ 4
010
fVCO ÷ 8
011
fVCO ÷ 16
100
fVCO ÷ 32
101
fVCO ÷ 64
Table 10. Post-PLL Divider NB
NB
Value
0fOUT, QB = fOUT, QA
1fOUT, QB = fOUT, QA ÷ 2
MPC92432
1360 MHz Dual Output LVPECL Clock Synthesizer
NETCOM
IDT 1360 MHz Dual Output LVPECL Clock Synthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC92432
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92432AER2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92432FA | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1360 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92433 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:1428 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92433AE | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92433AER2 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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