參數(shù)資料
型號(hào): MPC862T
廠商: Motorola, Inc.
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁(yè)數(shù): 67/88頁(yè)
文件大?。?/td> 1104K
代理商: MPC862T
MOTOROLA
MPC862/857T/857DSL Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
67
CPM Electrical Characteristics
11.12 I
2
C AC Electrical Specifications
Table 26 provides the I
2
C (SCL < 100 KHz) timings.
Table 27 provides the I
2
C (SCL > 100 kHz) timings.
Table 26. I
2
C Timing (SCL < 100 KH
Z
)
Num
Characteristic
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
SCL clock frequency (master)
1
0
100
kHz
200
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
1.5
100
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
μ
s
202
Bus free time between transmissions
4.7
203
Low period of SCL
4.7
204
High period of SCL
4.0
205
Start condition setup time
4.7
206
Start condition hold time
4.0
207
Data hold time
0
208
Data setup time
250
209
SDL/SCL rise time
1
210
SDL/SCL fall time
300
211
Stop condition setup time
4.7
Table 27. I
2
C Timing (SCL > 100 kH
Z
)
Num
Characteristic
Expression
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
SCL clock frequency (master)
1
fSCL
0
BRGCLK/48
Hz
200
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
1/(2.2 * fSCL)
s
203
Low period of SCL
1/(2.2 * fSCL)
s
204
High period of SCL
1/(2.2 * fSCL)
s
205
Start condition setup time
1/(2.2 * fSCL)
s
206
Start condition hold time
1/(2.2 * fSCL)
s
207
Data hold time
0
s
208
Data setup time
1/(40 * fSCL)
s
209
SDL/SCL rise time
1/(10 * fSCL)
s
210
SDL/SCL fall time
1/(33 * fSCL)
s
211
Stop condition setup time
1/2(2.2 * fSCL)
s
F
Freescale Semiconductor, Inc.
n
.
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