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參數(shù)資料
| 型號： | MPC862T |
| 廠商： | Motorola, Inc. |
| 英文描述： | Hardware Specifications |
| 中文描述： | 硬件規(guī)格 |
| 文件頁數(shù)： | 5/88頁 |
| 文件大小： | 1104K |
| 代理商： | MPC862T |
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MOTOROLA
MPC862/857T/857DSL Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
5
Features
One inter-integrated circuit (I
— Supports master and slave modes
— Multiple-master environment support
Time-slot assigner (TSA) (The MPC857DSL does not have the TSA)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, clocking
— Allows dynamic changes
— On the MPC862P and MPC862T, can be internally connected to six serial channels (four SCCs
and two SMCs); on the MPC857T, can be connected to three serial channels (one SCC and two
SMCs)
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC862/857T/857DSL or MC68360
PCMCIA interface
— Master (socket) interface, release 2.1 compliant
— Supports one or two PCMCIA sockets dependent upon whether ESAR functionality is enabled
— 8 memory or I/O windows supported
Low power support
— Full on—All units fully powered
— Doze—Core functional units disabled except time base decrementer, PLL, memory controller,
RTC, and CPM in low-power standby
— Sleep—All units disabled except RTC, PIT, time base, and decrementer with PLL active for fast
wake up
— Deep sleep—All units disabled including PLL except RTC, PIT, time base, and decrementer.
— Power down mode— All units powered down except PLL, RTC, PIT, time base and
decrementer
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data
— Supports conditions: =
≠
< >
— Each watchpoint can generate a break point internally
3.3 V operation with 5-V TTL compatibility except EXTAL and EXTCLK
357-pin plastic ball grid array (PBGA) package
Operation up to 100MHz
2
C) port
The MPC862/857T/857DSL is comprised of three modules that each use the 32-bit internal bus: the
MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). The
MPC862P/862T block diagram is shown in Figure 1. The MPC857T/857DSL block diagram is shown in
Figure 2.
F
Freescale Semiconductor, Inc.
n
.
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