參數(shù)資料
型號： MPC8572EVTAVNE
廠商： Freescale Semiconductor
文件頁數(shù)： 52/138頁
文件大小： 0K
描述： MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.5GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
20
Freescale Semiconductor
DDR2 and DDR3 SDRAM Controller
Table 12 provides the recommended operating conditions for the DDR SDRAM controller of the
MPC8572E when interfacing to DDR3 SDRAM.
Table 13 provides the DDR SDRAM controller interface capacitance for DDR2 and DDR3.
Table 14 provides the current draw characteristics for MVREFn.
6.2
DDR2 and DDR3 SDRAM Interface AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM controller interface. The
DDR controller supports both DDR2 and DDR3 memories. Note that although the minimum data rate for
most off-the-shelf DDR3 DIMMs available is 800 MHz, JEDEC specification does allow the DDR3 to run
at the data rate as low as 606 MHz. Unless otherwise specified, the AC timing specifications described in
Table 12. DDR3 SDRAM Interface DC Electrical Characteristics for GVDD(typ) = 1.5 V
Parameter/Condition
Symbol
Min
Typical
Max
Unit
I/O supply voltage
GVDD
1.425
1.575
V
1
I/O reference voltage
MVREFn
0.49
× GVDD
0.51
× GVDD
V2
Input high voltage
VIH
MVREFn + 0.100
GVDD
V—
Input low voltage
VIL
GND
MVREFn – 0.100
V
—
Output leakage current
IOZ
–50
50
μA3
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREFn is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREFn may not exceed ±1% of the DC value.
3. Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
Table 13. DDR2 and DDR3 SDRAM Interface Capacitance for GVDD(typ)=1.8 V and 1.5 V
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Input/output capacitance: DQ, DQS, DQS
CIO
6
8
pF
1, 2
Delta input/output capacitance: DQ, DQS, DQS
CDIO
—
0.5
pF
1, 2
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V (for DDR2), f = 1 MHz, TA = 25°C, VOUT =GVDD/2, VOUT
(peak-to-peak) = 0.2 V.
2. This parameter is sampled. GVDD = 1.5 V ± 0.075 V (for DDR3), f = 1 MHz, TA = 25°C, VOUT =GVDD/2, VOUT
(peak-to-peak) = 0.175 V.
Table 14. Current Draw Characteristics for MVREF n
Parameter / Condition
Symbol
Min
Max
Unit
Note
Current draw for MVREFn
DDR2 SDRAM
IMVREFn
—
1500
μA1
DDR3 SDRAM
1250
1. The voltage regulator for MVREFn must be able to supply up to 1500 μA or 1250 uA current for DDR2 or DDR3, respectively.
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