參數(shù)資料
型號: MPC8572EVTAVNE
廠商: Freescale Semiconductor
文件頁數(shù): 113/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
76
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
Figure 46. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 47. Single-Ended Reference Clock Input DC Requirements
15.2.3
Interfacing With Other Differential Signaling Levels
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (High-Speed Current Steering Logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (Low Voltage Differential Signaling)
can be used but may need to be AC-coupled due to the limited common mode input range allowed
(100 to 400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude,
additionally to AC-coupling.
SD
n_REF_CLK
SD
n_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax
< Vcm + 400 mV
Vmin
> Vcm – 400 mV
SD
n_REF_CLK
SD
n_REF_CLK
400 mV
< SDn_REF_CLK Input Amplitude < 800 mV
0V
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