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| 型號(hào)： | MPC8572EVTAVNE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 30/138頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.5GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤(pán) |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
125
System Design Information
AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
frequency. All traces should be kept short, wide and direct.
Figure 63. SerDes PLL Power Supply Filter
NOTE
AVDD_SRDSn should be a filtered version of SVDD_SRDSn.
NOTE
Signals on the SerDesn interface are fed from the XVDD_SRDSn power
plane.
21.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8572E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin
of the device. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD,
OVDD, GVDD, and LVDD, and GND power planes in the PCB, utilizing short traces to minimize
inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others
may surround the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
Additionally, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, TVDD, BVDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating
to ensure the quick response time necessary. They should also be connected to the power and ground
planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS
tantalum or Sanyo OSCON).
21.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes1 and SerDes2 blocks require a clean, tightly regulated source of power (SVDD_SRDSn and
XVDD_SRDSn) to ensure low jitter on transmit and reliable recovery of data in the receiver. An
appropriate decoupling scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
2.2 F 1
0.003 F
GND
1.0
Ω
AVDD_SRDSn
1. An 0805 sized capacitor is recommended for system initial bring-up.
SVDD_SRDSn
2.2 F 1
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