- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4032 > MPC8572ECLVTAULD (Freescale Semiconductor)MPU POWERQUICC III 1023FCPBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC8572ECLVTAULD |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 21/138頁(yè) |
| 文件大小： | 0K |
| 描述： | MPU POWERQUICC III 1023FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.333GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
117
Clocking
19 Clocking
This section describes the PLL configuration of the MPC8572E. Note that the platform clock is identical
to the core complex bus (CCB) clock.
19.1
Clock Ranges
Table 77 provides the clocking specifications for both processor cores.
The DDR memory controller can run in either synchronous or asynchronous mode. When running in
synchronous mode, the memory bus is clocked relative to the platform clock frequency. When running in
asynchronous mode, the memory bus is clocked with its own dedicated PLL with clock provided on
DDRCLK input pin. Table 78 provides the clocking specifications for the memory bus.
Table 77. MPC8572E Processor Core Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1067 MHz
1200 MHz
1333 MHz
1500 MHz
Min
Max
Min
Max
Min
Max
Min
Max
e500 core processor frequency
800
1067
800
1200
800
1333
800
1500
MHz
1, 2
CCB frequency
400
533
400
533
400
533
400
600
MHz
DDR Data Rate
400
667
400
667
400
667
400
800
MHz
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,” and Section 19.4,
“DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The processor core frequency speed bins listed also reflect the maximum platform (CCB) and DDR data rate frequency
supported by production test. Running CCB and/or DDR data rate higher than the limit shown above, although logically
possible via valid clock ratio setting in some condition, is not supported.
Table 78. Memory Bus Clocking Specifications
Characteristic
Min
Max
Unit
Notes
Memory bus clock frequency
200
400
MHz
1, 2, 3, 4
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,” and
Section 19.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The Memory bus clock refers to the MPC8572E memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5] output clocks, running
at half of the DDR data rate.
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. Refer to Section 19.4, “DDR/DDRCLK PLL
Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the
DDR data rate.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V06S25PF | IC SRAM 128KBIT 25NS 64TQFP |
| IDT70V06S20PF | IC SRAM 128KBIT 20NS 64TQFP |
| XF2B-5145-31A | CONN FPC 51POS 0.3MM PITCH SMD |
| IDT7035S20PF | IC SRAM 144KBIT 20NS 100TQFP |
| IDT7025S45PF | IC SRAM 128KBIT 45NS 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8572ECLVTAULE | 功能描述:微處理器 - MPU R211 Enc NoPb 1333LP Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572ECPXARLB | 功能描述:微處理器 - MPU RV1.1.1 SNPB 1067 EXT T RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572ECPXARLD | 功能描述:微處理器 - MPU PQ3 EXT TEMP 1067 MHz DDR 667 MHz RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572ECPXARLE | 功能描述:微處理器 - MPU R211 Enc SnPb 1067 Ext RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8572ECPXAULB | 功能描述:微處理器 - MPU RV1.1.1 SNPB 1333 EXT T RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。