參數(shù)資料
型號: MPC8555VTALD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 47/88頁
文件大?。?/td> 772K
代理商: MPC8555VTALD
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.1
Freescale Semiconductor
51
I2C
Figure 35 provides the test access port timing diagram.
Figure 35. Test Access Port Timing Diagram
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8555E.
12.1
I2C DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the I2C interface of the MPC8555E.
Table 39. I2C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage level
VIH
0.7
× OVDD
OVDD+ 0.3
V
Input low voltage level
VIL
–0.3
0.3
× OVDD
V
Low level output voltage
VOL
00.2
× OVDD
V1
Output fall time from VIH(min) to VIL(max) with a bus
capacitance from 10 to 400 pF
tI2KLKV
20 + 0.1
× CB
250
ns
2
Pulse width of spikes which must be suppressed by the
input filter
tI2KHKL
050
ns
3
Input current each I/O pin (input voltage is between 0.1
×
OVDD and 0.9 × OVDD(max)
II
–10
10
A4
Capacitance for each I/O pin
CI
—10
pF
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the
MPC8555E PowerQUICC III Integrated Communications Processor Reference Manual for information on the
digital filter used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
VM = Midpoint Voltage (OVDD/2)
VM
tJTIVKH
tJTIXKH
JTAG
External Clock
Output Data Valid
tJTKLOX
tJTKLOZ
tJTKLOV
Input
Data Valid
Output Data Valid
TDI, TMS
TDO
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