參數(shù)資料
型號(hào): MPC8555VTALD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù): 42/88頁(yè)
文件大?。?/td> 772K
代理商: MPC8555VTALD
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 3.1
Freescale Semiconductor
47
CPM
Figure 30. CPM I2C Bus Timing Diagram
The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k
respectively.
Data hold time 2
tSCLDX
2/(divider * fSCL)-
s
Data setup time2
tSDVCH
3/(divider * fSCL)-
s
SDA/SCL rise time
tSRISE
-1/(10 * fSCL)s
SDA/SCL fall time
tSFALL
-1/(33 * fSCL)s
Stop condition setup time
tSCHDH
2/(divider * fSCL)
-
s
1
FMAX = BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled
and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576
2
divider = fSCL/prescaler.
In master mode: divider=BRGCLK/(fSCL*prescaler)=2*(I2BRG[DIV]+3)
In slave mode: divider=BRGCLK/(fSCL*prescaler)
Table 36. CPM I2C Timing (fSCL=100KHz)
Characteristic
Expression
Frequency = 100KHz
Unit
Min
Max
SCL clock frequency (slave)
fSCL
100
KHz
SCL clock frequency (master)
fSCL
-
100
KHz
Bus free time between transmissions
tSDHDL
4.7
-
s
Low period of SCL
tSCLCH
4.7
-
s
High period of SCL
tSCHCL
4-
s
Start condition setup time
tSCHDL
2-
s
Start condition hold time
tSDLCL
3-
s
Data hold time
tSCLDX
2-
s
Data setup time
tSDVCH
3-
s
SDA/SCL rise time
tSRISE
-1
s
SDA/SCL fall time (master)
tSFALL
-
303
ns
Stop condition setup time
tSCHDH
2-
s
Table 35. I2C Timing (continued)
Characteristic
Expression
All Frequencies
Unit
Min
Max
SCL
SDA
tSDHDL
tSCLCH
tSCHCL
tSCHDL
tSDLCL
tSCLDX
tSDVCH
tSRISE
tSFALL
tSCHDH
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