參數(shù)資料
型號(hào): MPC8548ECPXATGB
廠商: Freescale Semiconductor
文件頁數(shù): 136/151頁
文件大小: 0K
描述: MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
85
Serial RapidIO
For each baud rate at which an LP-serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown
in Figure 52 with the parameters specified in Table 65 when measured at the output pins of the device and
the device is driving a 100-
± 5% differential resistive load. The output eye pattern of an LP-serial
Table 63. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output voltage
VO
–0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential output voltage
VDIFFPP
800
1600
mVp-p
Deterministic jitter
JD
0.17
UI p-p
Total jitter
JT
0.35
UI p-p
Multiple output skew
SMO
1000
ps
Skew at the transmitter output between lanes of a
multilane link
Unit interval
UI
400
ps
±100 ppm
Table 64. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output voltage
VO
–0.40
2.30
V
Voltage relative to COMMON of either signal
comprising a differential pair
Differential output voltage
VDIFFPP
800
1600
mVp-p
Deterministic jitter
JD
0.17
UI p-p
Total jitter
JT
0.35
UI p-p
Multiple output skew
SMO
1000
ps
Skew at the transmitter output between lanes of a
multilane link
Unit interval
UI
320
ps
±100 ppm
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