參數(shù)資料
型號: MPC8548ECPXATGB
廠商: Freescale Semiconductor
文件頁數(shù): 118/151頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊: MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
69
High-Speed Serial Interfaces (HSSI)
Figure 41. Differential Reference Clock Input DC Requirements (External AC-Coupled)
Figure 42. Single-Ended Reference Clock Input DC Requirements
16.2.3
Interfacing with Other Differential Signaling Levels
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed (100
to 400 mV) for DC-coupled connection.
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
NOTE
Figure 43 through Figure 46 below are for conceptual reference only. Due
to the fact that clock driver chip's internal structure, output impedance, and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the SerDes reference clock receiver requirement provided in
this document.
SD_REF_CLK
Vcm
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < Vcm + 400 mV
Vmin > Vcm – 400 mV
SD_REF_CLK
400 mV < SD_REF_CLK Input Amplitude < 800 mV
0 V
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