I2
參數(shù)資料
型號(hào)： MPC8548ECPXATGB
廠商： Freescale Semiconductor
文件頁數(shù)： 105/151頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.2GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
57
I2C
Figure 33 provides the AC test load for the I2C.
Figure 33. I2C AC Test Load
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1
OV
DD
—V
—
Noise margin at the HIGH level for each connected
device (including hysteresis)
VNH
0.2
OV
DD
—V
—
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the device provides a delay time of at least 300 ns for the SDA signal (see the VIH(min) of the SCL signal)
to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the
device acts as the I2C bus master while transmitting, the device drives both SCL and SDA. As long as the load on SCL and
SDA are balanced, the device would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA
output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the device
as a transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the desired
I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency is 400
kHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal 16):
I2C source clock frequency
333 MHz
266 MHz
200 MHz
133 MHz
FDR bit setting
0x2A
0x05
0x26
0x00
Actual FDR divider selected
896
704
512
384
Actual I2C SCL frequency generated
371 kHz
378 kHz
390 kHz
346 kHz
For the detail of I2C frequency calculation, see Determining the I2C Frequency Divider Ratio for SCL (AN2919). Note that the
I2C source clock frequency is half of the CCB clock frequency for the device.
3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. Guaranteed by design.
Table 46. I2C AC Electrical Specifications (continued)
Parameter
Symbol1
Min
Max
Unit
Notes
Output
Z0 = 50
OVDD/2
RL = 50
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