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| 型號(hào)： | MPC8545EPXANGB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 44/151頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 800MHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
138
Freescale Semiconductor
System Design Information
First, the board must have at least 10
10-nF SMT ceramic chip capacitors as close as possible to
the supply balls of the device. Where the board has blind vias, these capacitors must be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors must be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there must be a 1-F ceramic chip capacitor from each SerDes supply (SVDD and XVDD)
to the board ground plane on each side of the device. This must be done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there must be a 10-F, low equivalent
series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip
capacitor. This must be done for all SerDes supplies.
22.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs must be tied to VDD, TVDD, BVDD, OVDD, GVDD, and LVDD, as
required. All unused active high inputs must be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD, TVDD, BVDD,
OVDD, GVDD, LVDD, and GND pins of the device.
22.6
Pull-Up and Pull-Down Resistor Requirements
The device requires weak pull-up resistors (2–10 k
is recommended) on open drain type pins including
I2C pins and PIC (interrupt) pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 63. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion gives
unpredictable results.
The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1], and TEST_SEL/
TEST_SEL pins must be set to a proper state during POR configuration. See the pinlist table of the
individual device for more details
See the PCI 2.2 specification for all pull ups required for PCI.
22.7
Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 61). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN)/2.
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