參數(shù)資料
型號(hào)： MPC8545EPXANGB
廠商： Freescale Semiconductor
文件頁數(shù)： 110/151頁
文件大小： 0K
描述： MPU POWERQUICC III 783-PBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 800MHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
61
PCI/PCI-X
This table provides the PCI AC timing specifications at 66 MHz.
Figure 35 provides the AC test load for PCI and PCI-X.
Figure 35. PCI/PCI-X AC Test Load
Table 52. PCI AC Timing Specifications at 66 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
CLK to output valid
tPCKHOV
—
6.0
ns
2, 3
Output hold from CLK
tPCKHOX
2.0
—
ns
2, 10
CLK to output high impedance
tPCKHOZ
—
14
ns
2, 4, 11
Input setup to CLK
tPCIVKH
3.0
—
ns
2, 5, 10
Input hold from CLK
tPCIXKH
0
—
ns
2, 5, 10
REQ64 to HRESET 9 setup time
tPCRVRH
10
t
SYS
—
clocks
6, 7, 11
HRESET to REQ64 hold time
tPCRHRX
050
ns
7, 11
HRESET high to first FRAME assertion
tPCRHFV
10
—
clocks
8, 11
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI/PCI-X
timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference
(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI/PCI-X timing (PC) with respect to the time hard
reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OVDD/2 of the rising edge of SYSCLK or PCI_CLKn to 0.4 OVDD of the signal in question
for 3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 20, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Specifications.
9. The reset assertion timing requirement for HRESET is 100
s.
10.Guaranteed by characterization.
11.Guaranteed by design.
Output
Z0 = 50
LVDD/2
RL = 50
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