參數(shù)資料
型號(hào): MPC8360ECZUALFGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 667 MHz, RISC PROCESSOR, PBGA740
封裝: 37.50 X 37.50 MM, 1.46 MM HEIGHT, 1 MM PITCH, TBGA-740
文件頁(yè)數(shù): 18/102頁(yè)
文件大?。?/td> 606K
代理商: MPC8360ECZUALFGA
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
22
Freescale Semiconductor
DDR and DDR2 SDRAM AC Electrical Characteristics
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 21 and Table 22 provide the output AC timing specifications and measurement conditions for the DDR and DDR2
SDRAM interface.
Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Synchronous Mode
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter8
Symbol1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
610
ns
Skew between any MCK to ADDR/CMD
333 MHz
266 MHz
200 MHz
tAOSKEW
–1.0
–1.1
–1.2
0.2
0.3
0.4
ns
ADDR/CMD output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHAS
2.1
2.8
3.5
—ns
ADDR/CMD output hold with respect to MCK
333 MHz
266 MHz—DDR1
266 MHz—DDR2
200 MHz
tDDKHAX
2.0
2.7
2.8
3.5
—ns
MCS(n) output setup with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCS
2.1
2.8
3.5
—ns
MCS(n) output hold with respect to MCK
333 MHz
266 MHz
200 MHz
tDDKHCX
2.0
2.7
3.5
—ns
MCK to MDQS
tDDKHMH
–0.8
0.7
ns
5, 9
MDQ/MECC/MDM output setup with respect to MDQS
333 MHz
266 MHz
200 MHz
tDDKHDS,
tDDKLDS
0.7
1.0
1.2
—ns
MDQ/MECC/MDM output hold with respect to MDQS
333 MHz
266 MHz
200 MHz
tDDKHDX,
tDDKLDX
0.7
1.0
1.2
—ns
MDQS preamble start
tDDKHMP
–0.5
× tMCK – 0.6 –0.5 × tMCK + 0.6
ns
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