參數(shù)資料
型號: MPC8347ECVRAJD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA620
封裝: 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-620
文件頁數(shù): 14/102頁
文件大小: 1094K
代理商: MPC8347ECVRAJD
MPC8347E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
19
DDR SDRAM
Figure 6. DDR AC Test Load
Table 15 shows the DDR SDRAM measurement conditions.
Figure 7 shows the DDR SDRAM output timing diagram for source synchronous mode.
Figure 7. DDR SDRAM Output Timing Diagram for Source Synchronous Mode
Table 16 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings, which can be useful for a system utilizing the DLL.
These numbers are the result of simulations for one topology. The delay numbers will strongly depend on
the topology used. These delay numbers show the total delay for the address and command to arrive at the
DRAM devices. The actual delay could be different than the delays seen in simulation, depending on the
system topology. If a heavily loaded system is used, the DLL loop may need to be adjusted to meet setup
requirements at the DRAM.
Table 15. DDR SDRAM Measurement Conditions
Symbol
DDR
Unit
Notes
VTH
MVREF ± 0.31 V
V
1
VOUT
0.5
× GVDD
V2
Notes:
1. Data input threshold measurement point.
2. Data output measurement point.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
ADDR/CMD
tDDKLDS
tDDKHDS
MDQ[x]
MDQS[n]
MCK[n]
tMCK
tDDKLDX
tDDKHDX
D1
D0
tDDKHAX,tDDKHCX
Write A0
NOOP
tDDKHAS,tDDKHCS
tDDKHMH
tDDKHME
tDDKHMP
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