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| 型號： | MPC8309CVMAHFCA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 417 MHz, RISC PROCESSOR, PBGA489 |
| 封裝： | 19 X 19 MM, 1.61 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MAPBGA-489 |
| 文件頁數(shù)： | 64/81頁 |
| 文件大?。?/td> | 484K |
| 代理商： | MPC8309CVMAHFCA |
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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
Freescale Semiconductor
67
Clocking
Configuration chapter in the MPC8309 PowerQUICC II Pro Integrated Communications Processor
Reference Manual.
The qe_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF])
and the QUICC Engine PLL division factor (RCWL[CEPDF]) as the following equation:
qe_clk = (QE_CLK_IN × CEPMF)
(1 + CEPDF)
Eqn. 3
For more information, see the QUICC Engine PLL Multiplication Factor section and the “QUICC Engine
PLL Division Factor” section in the MPC8309 PowerQUICC II Pro Integrated Communications
Processor Reference Manual for more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(
2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LCLK). The LBC clock divider ratio is controlled by LCRR[CLKDIV].
For more information, see the LBC Bus Clock and Clock Ratios section in the MPC8309 PowerQUICC
II Pro Integrated Communications Processor Reference Manual.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset.
The following table specifies which units have a configurable clock frequency. For detailed description,
refer to the “System Clock Control Register (SCCR)” section in the MPC8309 PowerQUICC II Pro
Integrated Communications Processor Reference Manual.
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
The following table provides the maximum operating frequencies for the MPC8309 MAPBGA under
recommended operating conditions (see Table 2).
Table 56. Configurable Clock Units
Unit
Default Frequency
Options
I2C,SDHC, USB, DMA Complex
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Table 57. Operating Frequencies for MAPBGA
Characteristic1
Max Operating Frequency
Unit
e300 core frequency (core_clk)417
MHz
Coherent system bus frequency (csb_clk)167
MHz
QUICC Engine frequency (qe_clk)233
MHz
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8309EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications |
| MPC8309-KIT | 功能描述:開發(fā)板和工具包 - 其他處理器 For MPC8309 Ethernet USB I2C SPI RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8309-KIT | 制造商:Freescale Semiconductor 功能描述:MPC830x Processor Evaluation Kit |
| MPC8309-SOM | 功能描述:開發(fā)板和工具包 - 其他處理器 For MPC8309 Ethernet USB 16bit 32bit RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8309VMADDC | 制造商:Freescale Semiconductor 功能描述:MPC8309VMADDC - Bulk |
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