參數(shù)資料
型號: MPC8245TVV350D
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝: 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁數(shù): 42/60頁
文件大?。?/td> 674K
代理商: MPC8245TVV350D
MOTOROLA
MPC8245 Integrated Processor Hardware Specications
47
System Design Information
The arrangement shown in Figure 26 allows the COP to independently assert HRESET or TRST, while
ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used,
TRST should be tied to HRESET so that it is asserted when the system reset signal (HRESET) is asserted
ensuring that the JTAG scan chain is initialized during power-on.
The COP header shown in Figure 26 adds many benets—breakpoints, watchpoints, register and memory
examination/modication, and other standard debugger features are possible through this interface—and
can be as inexpensive as an unpopulated footprint for a header to be added when needed.
The COP interface has a standard header for connection to the target system, based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header).
There is no standardized way to number the COP header shown in Figure 26; consequently, many different
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 26 is common to all known emulators.
相關PDF資料
PDF描述
MPC8245TVV300D 32-BIT, 300 MHz, RISC PROCESSOR, PBGA352
MPC8250ACZQIHBX 32-BIT, 200 MHz, RISC PROCESSOR, PBGA516
MPC8250AVVLHDX 32-BIT, 250 MHz, RISC PROCESSOR, PBGA480
MPC8250AVRIHBX 32-BIT, 200 MHz, RISC PROCESSOR, PBGA516
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