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參數(shù)資料
| 型號(hào)： | MPC8245TVV350D |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352 |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 674K |
| 代理商： | MPC8245TVV350D |
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26
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
Electrical and Thermal Characteristics
Figure 14. I2C Timing Diagram I
Table 14. I2C Output AC Timing Specications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
(FDR[5] == 0)
× (DFDR/16)/2N + (FDR[5]
== 1)
× (DFDR/16)/2M
—
CLKs
1, 2, 3
2
Clock low period
DFDR/2
—
CLKs
1, 2, 3
3
SCL/SDA rise time
(from 0.5 V to 2.4 V)
—
ms
4
Data hold time
8.0 + (16
× 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1, 2, 3
5
SCL/SDA fall time
(from 2.4 V to 0.5 V)
—< 5
ns
5
6
Clock high time
DFDR/2
—
CLKs
1, 2, 3
7
Data setup time
(MPC8245 as a master only)
(DFDR/2) – (output data hold time)
—
CLKs
1, 3
8
Start condition setup time
(for repeated start condition only)
DFDR + (output start condition hold time)
—
CLKs
1, 2, 3
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital lter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualied signals. The
qualied SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualied SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 15.
3. DFDR is the decimal divider number indexed by FDR[5:0] value. Refer to Table 10-5 in the MPC8245 Integrated
Processor User’s Manual. FDR[x] refers to bit x of the frequency divider register I2CFDR. N is equal to a variable
number that would make the result of the divide (data hold time value) equal to a number less than 16. M is equal
to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9.
4. Since SCL and SDA are open-drain type outputs, which the MPC8245 can only drive low, the time required for SCL
or SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
5. Specied at a nominal 50 pF load.
SCL
SDA
VM
6
2
1
4
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