參數(shù)資料
型號： MPC8245TVV350D
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件頁數(shù)： 17/60頁
文件大?。?/td> 674K
代理商： MPC8245TVV350D
24
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
Electrical and Thermal Characteristics
1.4.3.4
I2C AC Timing Specications
Table 12 provides the I2C input AC timing specications for the MPC8245 at recommended operating
conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
Table 12. I2C Input AC Timing Specications
Num
Characteristic
Min
Max
Unit
Notes
1
Start condition hold time
4.0
—
CLKs
1, 2
2
Clock low period
(time before the MPC8245 will drive SCL
low as a transmitting slave after detecting
SCL low as driven by an external master)
8.0 + (16
× 2FDR[4:2]) × (5 –
4({FDR[5],FDR[1]} == b’10) –
3({FDR[5],FDR[1]} == b’11) –
2({FDR[5],FDR[1]} == b’00) –
1({FDR[5],FDR[1]} == b’01))
—
CLKs
1, 2, 4, 5
3
SCL/SDA rise time (from 0.5 V to 2.4 V)
—
1
ms
4
Data hold time
0
—
ns
2
5
SCL/SDA fall time (from 2.4 V to 0.5 V)
—
1
ms
6
Clock high period
(time needed to either receive a data bit or
generate a START or STOP)
5.0
—
CLKs
1, 2, 5
7
Data setup time
3.0
—
ns
3
8
Start condition setup time (for repeated
start condition only)
4.0
—
CLKs
1,2
9
Stop condition setup time
4.0
—
CLKs
1, 2
Notes:
1. Units for these specications are in SDRAM_CLK units.
2. The actual values depend on the setting of the digital lter frequency sampling rate (DFFSR) bits in the frequency
divider register I2CFDR. Therefore, the noted timings in the above table are all relative to qualied signals. The
qualied SCL and SDA are delayed signals from what is seen in real time on the I2C bus. The qualied SCL, SDA
signals are delayed by the SDRAM_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK clock. The resulting delay
value is added to the value in the table (where this note is referenced). See Figure 15.
3. Timing is relative to the sampling clock (not SCL).
4. FDR[x] refers to the frequency divider register I2CFDR bit x.
5. Input clock low and high periods in combination with the FDR value in the frequency divider register (I2CFDR)
determine the maximum I2C input frequency. See Table 13.
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