參數(shù)資料
型號(hào)： MPC8245LZU350X
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 350 MHz, RISC PROCESSOR, PBGA352
封裝： 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, CAVITY DOWN, TBGA-352
文件頁數(shù)： 51/60頁
文件大?。?/td> 620K
代理商： MPC8245LZU350X
MPC8245 Integrated Processor Hardware Specications
55
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Document Revision History
0.2
Changed core supply voltage to 2.0 ± 100 mV in Section 1.3, “General Parameters.” (Supply voltage of 1.8
± 100 mV is no longer recommended.)
Changed rows 2, 5, and 6 of Table 2 to 2.0 ± 100 mV in the “Recommended Value” column.
Changed the power consumption numbers in Table 5 to reect the power values for Vdd = 2.0 V. (Notes 2,
3, 4, and 5 of the table were also updated to reect the new value of Vdd.)
Updated Table 7 for Vdd/AVdd/AVdd2 to 2.0 ± 100 mV.
Table 8: Vdd/AVdd/AVdd2 was changed to 2.0 volts for both CPU frequency offerings. Note 2 was updated
by removing the “at reduced voltage...” statement.
Table 10: Update maximum time of the rows 12a0 through 12a3.
Table 16: Fixed overbars for the active-low signals. Changed pin type information for Vdd, AVdd, and
AVdd2 to 2.0 V.
Changed note 16 of Table 17 to a value of 2.0 V for Vdd/AVdd/AVdd2.
Removed second sentence of the second paragraph in Section 1.7.2, “Power Supply Voltage
Sequencing,” because it referenced information about a 1.8-V design.
Removed reference to 1.8 volts in third sentence of Section 1.7.8, “MPC8245 Compatibility with
0.3
Section 1.4.1.5: Changed Max-FP value for 33/133/266 of Table 5, from 2.3 to 2.1 watts, to represent
characterizaiton data. Changed note 4 to say Vdd=2.1 for power measurements (for 2 volt part). Changed
numbers for maximum I/O power supplies for OVdd and GVdd to represent characterization data.
Section 1.4.3.1: Added four graphs (Figures 5-8) and description for DLL Locking Range vs. Frequency of
Operation to replace gure 5 of rev 0.2 document.
Section 1.4.3.2: Added row (item 11: Tsu - SDRAM_SYNC_IN to PCI_SYNC_IN timing) to Table 9, to
include offset change requirement.
Section 1.5.3: Changed note 4 of PLL_CFG pins in Table 16 to note 20.
Section 1.7.2: Added diode (MUR420) to Fig. 27, Voltage Sequencing circuit. This is to compensate for
voltage extremes in design.
Section 1.7.5: Addes sentence with regards to SDRAM_SYNC_IN to PCI_SYNC_IN timing requirement
(Tsu) as a connection recommendation.
Section 1.7.8 : Mention of Tsu offset timing, and driver capability differences between the MPC8240 and
the MPC8245.
0.4
Section 1.2: Changed Features list (format) to match with the features list of the 8245 user’s manual.
Section 1.4.1.2 Updated Table 2 to include 1.8 ± 100mV numbers.
Section 1.4.3: Changed Table 7 to include new part offerings of 333 MHz and 350 MHz. Added rows to
include VCO frequency ranges for all parts for both memory VCO and CPU VCO.
Section 1.4.1.5: Updated Power consumption table to include 1.8 V (Vdd) and higher frequency numbers.
Section 1.4.3: Updated Table 7 to include higher frequency offerings and CPU VCO frequency range.
Section 1.4.3.1: Changed lettering to caps for DLL_EXTEND and DLL_MAX_DELAY in graph description
section.
Section 1.4.3.2: Changed name of item 11 from “Tsu - SDRAM_SYNC_IN to PCI_SYNC_IN time” to “Tos -
SDRAM_SYNC_IN to sys_logic_clk offset time”. Changed name to Tos in note 7 as well.
Section 1.6: Updated notes of Table 17. Included minimum and maximum VCO numbers for memory
VCO. Changed note 13 for ocation of PLL_CFG[0-4] to correct bits location. Bits 7– 4 of register offset
<0xE2>. Added Table 18 to cover PLL conguration of higher frequency part offerings.
Section: 1.7 Changed frequency ranges for reference numbers 0, 9, 10, and 17, for the 300 MHz part, to
inlude the higher memory bus frequencies when operating at lower CPU bus frequencies. Added Table 18
to include PLL congurations for the 333 MHz and the 350 MHz CPU part offerings. Added VCO
multiplers in Tables 17 and 18.
Section 1.7.8: Changed Tsu - SDRAM_SYNC_IN to PCI_SYNC_IN time” to “Tos - SDRAM_SYNC_IN to
sys_logic_clk offset time.”
Section 1.7.10: Added vendor (Cool Innovations, Inc.) to list of Heat Sink vendors.
Table 19. Document Revision History (Continued)
Revision
Substantive Change(s)
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MPC8245RZU400D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Part Number Specification for the MPC8245ARZUnnnX Series
MPC8245TVV266D 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245TVV300D 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245TVV333D 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8245TVV350D 功能描述:微處理器 - MPU INTEGRATED HOST PROC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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